EP2SGX60EF1152C3N Altera, EP2SGX60EF1152C3N Datasheet - Page 119

• Manufacturer Part Number: EP2SGX60EF1152C3N
• Description: IC STRATIX II GX 60K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX60EF1152C3N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 534
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2181

Altera Corporation
October 2007
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The IOE in Stratix II GX devices contains a bidirectional I/O buffer, six
registers, and a latch for a complete embedded bidirectional single data
rate or DDR transfer.
The IOE contains two input registers (plus a latch), two output registers,
and two output enable registers. You can use both input registers and the
latch to capture DDR input and both output registers to drive DDR
outputs. Additionally, you can use the output enable (OE) register for fast
clock-to-output enable timing. The negative edge-clocked OE register is
used for DDR SDRAM interfacing. The Quartus II software automatically
duplicates a single OE register that controls multiple output or
bidirectional pins.
Open-drain outputs
DQ and DQS I/O pins
Double data rate (DDR) registers
Figure 2–76
shows the Stratix II GX IOE structure.
Stratix II GX Device Handbook, Volume 1
Stratix II GX Architecture
2–111