EP2SGX60EF1152C3N Altera, EP2SGX60EF1152C3N Datasheet - Page 125
EP2SGX60EF1152C3N
Manufacturer Part Number
EP2SGX60EF1152C3N
Description
IC STRATIX II GX 60K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX60EF1152C3N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2181
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX60EF1152C3N
Manufacturer:
ATMEL
Quantity:
1 420
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Figure 2–81. Stratix II GX IOE in Bidirectional I/O Configuration
Notes to
(1)
(2)
Altera Corporation
October 2007
Column, Row,
Interconnect
or Local
All input signals to the IOE can be inverted at the IOE.
The optional PCI clamp is only available on column I/O pins.
ioe_clk[7..0]
Figure
2–81:
clkout
clkin
oe
ce_out
aclr/apreset
ce_in
sclr/spreset
Chip-Wide Reset
The Stratix II GX device IOE includes programmable delays that can be
activated to ensure input IOE register-to-logic array register transfers,
input pin-to-logic array register transfers, or output IOE register-to-pin
transfers.
Output Register
Input Register
OE Register
D
CLRN/PRN
ENA
ENA
D
CLRN/PRN
D
CLRN/PRN
ENA
Q
Q
Q
Drive Strength Control
Open-Drain Output
Pin Delay
Output
Input Register Delay
Logic Array Delay
Stratix II GX Device Handbook, Volume 1
Input Pin to
Input Pin to
Note (1)
OE Register
t
CO
Delay
V
Stratix II GX Architecture
CCIO
PCI Clamp (2)
V
CCIO
Bus-Hold
Termination
Circuit
On-Chip
Programmable
Pull-Up
Resistor
2–117
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