EP3C40F780I7 Altera, EP3C40F780I7 Datasheet - Page 198

• Manufacturer Part Number: EP3C40F780I7
• Description: IC CYCLONE III FPGA 40K 780 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C40F780I7

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1161216
• Number Of I /o: 535
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 39600
• # I/os (max): 535
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 39600
• Ram Bits: 1161216
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

9–38
Cyclone III Device Handbook, Volume 1
Figure 9–16
family is receiving the same configuration data.
Figure 9–16. Multi-Device PS Configuration When Both Devices Receive the Same Data
Notes to
(1) The pull-up resistor must be connected to a supply that provides an acceptable input signal for all devices in the
(2) The nCEO pins of both devices are left unconnected or used as user I/O pins when configuring the same
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0],
(4) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[0] and DCLK must fit the maximum overshoot
(MAX II Device or
Microprocessor)
External Host
chain. V
configuration data into multiple devices.
refer to
equation outlined in
ADDR
Figure
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Memory
Table 9–7 on page
CC
DATA[0]
must be high enough to meet the V
shows a multi-device PS configuration when both Cyclone III device
9–16:
10 k
V
“Configuration and JTAG Pin I/O Requirements” on page
CCIO
9–11. Connect the MSEL pins directly to V
(1) V
10 k
CCIO
GND
(1)
Buffers (4)
Cyclone III Device Family
IH
CONF_DONE
nSTATUS
nCE
DATA[0] (4)
nCONFIG
DCLK (4)
specification of the I/O on the device and the external host.
MSEL[3..0]
nCEO
(3)
N.C. (2)
CCA
or ground.
© December 2009 Altera Corporation
9–7.
GND
Cyclone III Device Family
CONF_DONE
nSTATUS
nCE
DATA[0] (4)
nCONFIG
DCLK (4)
Configuration Features
MSEL[3..0]
nCEO
N.C. (2)
(3)