EP3CLS70F484I7N Altera, EP3CLS70F484I7N Datasheet - Page 112
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP3CLS70F484I7N
Manufacturer Part Number
EP3CLS70F484I7N
Description
IC FPGA CYCIII LS 70K 484-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3CLS70F484I7N.pdf
(274 pages)
Specifications of EP3CLS70F484I7N
Number Of Logic Elements/cells
70208
Number Of Labs/clbs
4388
Total Ram Bits
3068928
Number Of I /o
278
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Cyclone III LS
Number Of Logic Blocks/elements
70208
# I/os (max)
278
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
70208
Ram Bits
3068928
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP3C5F256C8N PDF datasheet
- EP3C5F256C8N PDF datasheet #2
- EP3C5F256C8N PDF datasheet #3
- EP3C5F256C8N PDF datasheet #4
- EP3C5F256C8N PDF datasheet #5
- EP3CLS70F484I7N PDF datasheet #6
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- Download datasheet (6Mb)
6–12
Table 6–4. Cyclone III Device Family Supported I/O Standards and Constraints (Part 1 of 2)
Cyclone III Device Handbook, Volume 1
3.3-V LVTTL,
3.3-V LVCMOS
3.0-V LVTTL,
3.0-V LVCMOS
2.5-V LVTTL /
LVCMOS
1.8-V LVTTL /
LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
SSTL-2 Class I,
SSTL-2 Class II
SSTL-18 Class I,
SSTL-18 Class II
HSTL-18 Class I,
HSTL-18 Class II
HSTL-15 Class I,
HSTL-15 Class II
HSTL-12 Class I
HSTL-12 Class II
PCI and PCI-X
Differential SSTL-2
Class I or Class II
Differential SSTL-18
Class I or Class II
Differential HSTL-18
Class I or Class II
Differential HSTL-15
Class I or Class II
Differential HSTL-12
Class I or Class II
PPDS
LVDS
I/O Standard
(7)
(3)
(1)
(1)
(6)
Single-ended JESD8-B
Single-ended JESD8-B
Single-ended JESD8-5
Single-ended JESD8-7
Single-ended JESD8-11
Single-ended JESD8-12A
Voltage
referenced
Voltage
referenced
Voltage
referenced
Voltage
referenced
Voltage
referenced
Voltage
referenced
Single-ended
Differential
(2)
Differential
(2)
Differential
(2)
Differential
(2)
Differential
(2)
Differential
Differential
Table 6–4
I/O pins support them.
Type
lists I/O standards supported by the Cyclone III device family and which
JESD8-9A
JESD815
JESD8-6
JESD8-6
JESD8-16A
JESD8-16A
JESD8-9A
JESD815
JESD8-6
JESD8-6
JESD8-16A
Standard
Support
—
—
—
3.3/3.0/2.5
3.3/3.0/2.5
3.3/3.0/2.5
1.8/1.5
1.8/1.5
Input
1.2
2.5
1.8
1.8
1.5
1.2
1.2
3.0
2.5
1.8
1.8
1.5
1.2
2.5
V
—
—
—
—
—
—
C CIO
Level (in V)
Output
3.3
3.0
2.5
1.8
1.5
1.2
2.5
1.8
1.8
1.5
1.2
1.2
3.0
2.5
1.8
1.8
1.5
1.2
2.5
2.5
—
—
—
—
—
Chapter 6: I/O Features in the Cyclone III Device Family
CLK,
DQS
Top and Bottom I/O Pins
v
v
v
v
v
v
v
v
v
v
v
v
v
—
v
—
v
—
v
—
v
—
v
—
v
PLL_OUT
© December 2009 Altera Corporation
v
v
v
v
v
v
v
v
v
v
v
v
v
v
—
v
—
v
v
v
v
v
—
—
—
User
Pins
I/O
v
v
v
v
v
v
v
v
v
v
v
v
v
—
—
—
—
—
—
—
—
—
—
v
v
CLK,
Left and Right
DQS
I/O Standards
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
—
—
—
—
—
—
—
I/O Pins
User I/O
Pins
v
v
v
v
v
v
v
v
v
v
v
—
v
—
—
—
—
—
—
—
—
—
—
v
v
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