EP3CLS70F484I7N Altera, EP3CLS70F484I7N Datasheet - Page 235
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EP3CLS70F484I7N
Manufacturer Part Number
EP3CLS70F484I7N
Description
IC FPGA CYCIII LS 70K 484-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3CLS70F484I7N.pdf
(274 pages)
Specifications of EP3CLS70F484I7N
Number Of Logic Elements/cells
70208
Number Of Labs/clbs
4388
Total Ram Bits
3068928
Number Of I /o
278
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Cyclone III LS
Number Of Logic Blocks/elements
70208
# I/os (max)
278
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
70208
Ram Bits
3068928
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Design Security
Cyclone III LS Design Security Solution
© December 2009
f
f
Altera Corporation
For more information about the battery specifications, refer to the
Data Sheet
Cyclone III LS devices are SRAM-based devices. To provide design security,
Cyclone III LS devices require a 256-bit volatile key for configuration bitstream
encryption.
The Cyclone III LS design security feature provides routing architecture optimization
for design separation flow with the Quartus II software. Design separation flow
achieves both physical and functional isolation between design partitions.
For more information about the design separation flow, refer to
Design Separation Flow.
You can carry out secure configuration in Steps 1–3, as shown in
1. Generate the encryption key programming file and encrypt the configuration data.
2. Program the volatile key into the Cyclone III LS device.
3. Configure the Cyclone III LS device.
Figure 9–31. Cyclone III LS Secure Configuration Flow
Note to
(1) Step 1, Step 2, and Step 3 correspond to the procedure detailed in
The Quartus II configuration software uses the user-defined 256-bit volatile keys
to generate a key programming file and an encrypted configuration file. The
encrypted configuration file is stored in an external memory, such as a flash
memory or a configuration device.
Program the user-defined 256-bit volatile keys into the Cyclone III LS device
through the JTAG interface.
At system power-up, the external memory device sends the encrypted
configuration file to the Cyclone III LS device.
Figure
Step 1. Generate the Encryption Key Programming File
Configuration
Data
chapter.
9–31:
Encrypt Configuration Data and Store in External Memory
Quartus II
Volatile Key
Encryptor
AES
Programming File
Configuration
Encryption Key
Encrypted
Data
Configuration
Encrypted
Memory
Storage
Data
(Note 1)
“Cyclone III LS Design Security
Configuration
Step 2. Program Volatile Key into
Cyclone III LS Device
Encrypted
Step 3. Configure the Cyclone III LS Device
Using Encrypted Configuration Data
Data
Cyclone III Device Handbook, Volume 1
AN 567: Quartus II
Figure
Key Storage
Volatile Key
Cyclone III LS Device
Decryptor
Volatile
FPGA
AES
9–31:
Solution”.
9–75
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