EP3CLS70F484I7N Altera, EP3CLS70F484I7N Datasheet - Page 38

• Manufacturer Part Number: EP3CLS70F484I7N
• Description: IC FPGA CYCIII LS 70K 484-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3CLS70F484I7N

• Number Of Logic Elements/cells: 70208
• Number Of Labs/clbs: 4388
• Total Ram Bits: 3068928
• Number Of I /o: 278
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III LS
• Number Of Logic Blocks/elements: 70208
• # I/os (max): 278
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 70208
• Ram Bits: 3068928
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

3–2
Cyclone III Device Handbook, Volume 1
f
Table 3–1
Table 3–1. Summary of M9K Memory Features
For information about the number of M9K memory blocks for the Cyclone III device
family, refer to the
Configurations (depth × width)
Parity bits
Byte enable
Packed mode
Address clock enable
Single-port mode
Simple dual-port mode
True dual-port mode
Embedded shift register mode
ROM mode
FIFO buffer
Simple dual-port mixed width support
True dual-port mixed width support
Memory initialization file (.mif)
Mixed-clock mode
Power-up condition
Register asynchronous clears
Latch asynchronous clears
Write or read operation triggering
Same-port read-during-write
Mixed-port read-during-write
Notes to
(1) FIFO buffers and embedded shift registers that require external logic elements (LEs) for implementing control
(2) Width modes of ×32 and ×36 are not available.
logic.
Table
lists the features supported by the M9K memory
(1)
3–1:
Feature
Cyclone III Device Family Overview
(1)
(2)
Read address registers and output registers only
Chapter 3: Memory Blocks in the Cyclone III Device Family
Outputs set to Old Data or Don’t Care
Outputs set to Old Data or New Data
Write and read: Rising clock edges
chapter.
Output latches only
Outputs cleared
M9K Blocks
© December 2009 Altera Corporation
8192 × 1
4096 × 2
2048 × 4
1024 × 8
1024 × 9
512 × 16
512 × 18
256 × 32
256 × 36
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Overview