EP2S30F484C4N Altera, EP2S30F484C4N Datasheet - Page 13
![IC STRATIX II FPGA 30K 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP2S30F484C4N
Manufacturer Part Number
EP2S30F484C4N
Description
IC STRATIX II FPGA 30K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F484C4N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
342
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1891
EP2S30F484C4N
EP2S30F484C4N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F484C4N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2S30F484C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 13 of 238
- Download datasheet (3Mb)
Figure 2–3. Direct Link Connection
Altera Corporation
May 2007
block, DSP block, or IOE output
Direct link interconnect from
left LAB, TriMatrix memory
interconnect
Direct link
to left
Interconnect
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its ALMs.
The control signals include three clocks, three clock enables, two
asynchronous clears, synchronous clear, asynchronous preset/load, and
synchronous load control signals. This gives a maximum of 11 control
signals at a time. Although synchronous load and clear signals are
generally used when implementing counters, they can also be used with
other functions.
Each LAB can use three clocks and three clock enable signals. However,
there can only be up to two unique clocks per LAB, as shown in the LAB
control signal generation circuit in
enable signals are linked. For example, any ALM in a particular LAB
using the labclk1 signal also uses labclkena1. If the LAB uses both
the rising and falling edges of a clock, it also uses two LAB-wide clock
signals. De-asserting the clock enable signal turns off the corresponding
LAB-wide clock.
Each LAB can use two asynchronous clear signals and an asynchronous
load/preset signal. By default, the Quartus II software uses a NOT gate
push-back technique to achieve preset. If you disable the NOT gate
push-up option or assign a given register to power up high using the
Quartus II software, the preset is achieved using the asynchronous load
Local
Figure
Stratix II Device Handbook, Volume 1
ALMs
2–4. Each LAB's clock and clock
Direct link
interconnect
to right
Direct link interconnect from
right LAB, TriMatrix memory
block, DSP block, or IOE output
Stratix II Architecture
2–5
Related parts for EP2S30F484C4N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![DK-CYCII-2C20N](/photos/9/20/92074/mfgdk-cycii-2c20nboard_tmb.jpg)
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610IPC-25](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-30](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-12](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10A](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![P85C224-66](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP320PC](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP2A15B724C7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-25T](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: