EP2S30F484C4N Altera, EP2S30F484C4N Datasheet - Page 159
![IC STRATIX II FPGA 30K 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP2S30F484C4N
Manufacturer Part Number
EP2S30F484C4N
Description
IC STRATIX II FPGA 30K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F484C4N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
342
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1891
EP2S30F484C4N
EP2S30F484C4N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F484C4N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2S30F484C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Altera Corporation
April 2011
4.
5.
The Quartus II software reports the timing with the conditions shown in
Table 5–34
circuit that is represented by the output timing of the Quartus II software.
Figure 5–4. Output Delay Timing Reporting Setup Modeled by Quartus II
Notes to
(1)
(2)
(3)
Figures 5–5
output enable timing.
Record the time to V
Compare the results of steps 2 and 4. The increase or decrease in
delay should be added to or subtracted from the I/O Standard
Output Adder delays to yield the actual worst-case propagation
delay (clock-to-output) of the PCB trace.
Output pin timing is reported at the output pin of the FPGA device. Additional
delays for loading and board trace delay need to be accounted for with IBIS model
simulations.
V
V
CCPD
CCINT
Output
Buffer
Figure
V
GND
CCIO
is 3.085 V unless otherwise specified.
is 1.12 V unless otherwise specified.
using the above equation.
and
5–4:
Output
5–6
V
show the measurement setup for output disable and
MEAS
MEAS
R
.
S
GND
V
TT
R
C
Stratix II Device Handbook, Volume 1
Figure 5–4
T
L
DC & Switching Characteristics
shows the model of the
Output
Output
p
n
R
D
5–23
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