EP2S30F484C4N Altera, EP2S30F484C4N Datasheet - Page 32
![IC STRATIX II FPGA 30K 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP2S30F484C4N
Manufacturer Part Number
EP2S30F484C4N
Description
IC STRATIX II FPGA 30K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F484C4N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
342
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1891
EP2S30F484C4N
EP2S30F484C4N
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F484C4N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2S30F484C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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MultiTrack Interconnect
2–24
Stratix II Device Handbook, Volume 1
R24 row interconnects span 24 LABs and provide the fastest resource for
long row connections between LABs, TriMatrix memory, DSP blocks, and
Row IOEs. The R24 row interconnects can cross M-RAM blocks. R24 row
interconnects drive to other row or column interconnects at every fourth
LAB and do not drive directly to LAB local interconnects. R24 row
interconnects drive LAB local interconnects via R4 and C4 interconnects.
R24 interconnects can drive R24, R4, C16, and C4 interconnects.
The column interconnect operates similarly to the row interconnect and
vertically routes signals to and from LABs, TriMatrix memory, DSP
blocks, and IOEs. Each column of LABs is served by a dedicated column
interconnect. These column resources include:
■
■
■
■
■
Stratix II devices include an enhanced interconnect structure in LABs for
routing shared arithmetic chains and carry chains for efficient arithmetic
functions. The register chain connection allows the register output of one
ALM to connect directly to the register input of the next ALM in the LAB
for fast shift registers. These ALM to ALM connections bypass the local
interconnect. The Quartus II Compiler automatically takes advantage of
these resources to improve utilization and performance.
shows the shared arithmetic chain, carry chain and register chain
interconnects.
Shared arithmetic chain interconnects in an LAB
Carry chain interconnects in an LAB and from LAB to LAB
Register chain interconnects in an LAB
C4 interconnects traversing a distance of four blocks in up and down
direction
C16 column interconnects for high-speed vertical routing through
the device
Altera Corporation
Figure 2–17
May 2007
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