EP2S30F484C4N Altera, EP2S30F484C4N Datasheet - Page 62
![IC STRATIX II FPGA 30K 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP2S30F484C4N
Manufacturer Part Number
EP2S30F484C4N
Description
IC STRATIX II FPGA 30K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F484C4N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
342
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1891
EP2S30F484C4N
EP2S30F484C4N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F484C4N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2S30F484C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 62 of 238
- Download datasheet (3Mb)
PLLs & Clock Networks
2–54
Stratix II Device Handbook, Volume 1
1
Figures 2–37
clock, regional clock, and PLL external clock output, respectively.
Figure 2–37. Global Clock Control Blocks
Notes to
(1)
(2)
These clock select signals can be dynamically controlled through internal logic
when the device is operating in user mode.
These clock select signals can only be set through a configuration file (.sof or .pof)
and cannot be dynamically controlled during user mode operation.
Figure
CLKSELECT[1..0]
When using the global or regional clock control blocks in
Stratix II devices to select between multiple clocks or to enable
and disable clock networks, be aware of possible narrow pulses
or glitches when switching from one clock signal to another. A
glitch or runt pulse has a width that is less than the width of the
highest frequency input clock signal. To prevent logic errors
within the FPGA, Altera recommends that you build circuits
that filter out glitches and runt pulses.
(1)
This multiplexer supports
User-Controllable
Dynamic Switching
through
PLL Counter
2–37:
Outputs
2–39
2
2
show the clock control block for the global
CLKp
Pins
2
Enable/
Disable
GCLK
CLKn
Pin
Internal
Logic
Internal
Static Clock Select
Logic
Altera Corporation
(2)
May 2007
Related parts for EP2S30F484C4N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![DK-CYCII-2C20N](/photos/9/20/92074/mfgdk-cycii-2c20nboard_tmb.jpg)
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610IPC-25](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-30](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-12](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10A](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![P85C224-66](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP320PC](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP2A15B724C7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-25T](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: