EP2SGX30CF780C3N Altera, EP2SGX30CF780C3N Datasheet - Page 140
![IC STRATIX II GX 30K 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP2SGX30CF780C3N
Manufacturer Part Number
EP2SGX30CF780C3N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX30CF780C3N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
33880
# I/os (max)
361
Frequency (max)
816.9MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1926
EP2SGX30CF780C3N
EP2SGX30CF780C3N
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I/O Structure
2–132
Stratix II GX Device Handbook, Volume 1
f
f
f
f
f
For more information on tolerance specifications for differential on-chip
termination, refer to the
volume 1 of the Stratix II GX Device Handbook.
On-Chip Series Termination without Calibration
Stratix II GX devices support driver impedance matching to provide the
I/O driver with controlled output impedance that closely matches the
impedance of the transmission line. As a result, reflections can be
significantly reduced. Stratix II GX devices support on-chip series
termination for single-ended I/O standards with typical R
25 and 50 Ω . Once matching impedance is selected, current drive
strength is no longer selectable.
standards that support on-chip series termination without calibration.
For more information about series on-chip termination supported by
Stratix II GX devices, refer to the
Stratix II GX Devices
Handbook.
For more information about tolerance specifications for on-chip
termination without calibration, refer to the
Characteristics
On-Chip Series Termination with Calibration
Stratix II GX devices support on-chip series termination with calibration
in column I/O pins in top and bottom banks. There is one calibration
circuit for the top I/O banks and one circuit for the bottom I/O banks.
Each on-chip series termination calibration circuit compares the total
impedance of each I/O buffer to the external 25-Ω or 50-Ω resistors
connected to the RUP and RDN pins, and dynamically enables or disables
the transistors until they match. Calibration occurs at the end of device
configuration. Once the calibration circuit finds the correct impedance, it
powers down and stops changing the characteristics of the drivers.
For more information about series on-chip termination supported by
Stratix II GX devices, refer to the
Stratix II GX Devices
Handbook.
For more information about tolerance specifications for on-chip
termination with calibration, refer to the
chapter in volume 1 of the Stratix II GX Device Handbook.
chapter in volume 1 of the Stratix II GX Device Handbook.
chapter in volume 2 of the Stratix II GX Device
chapter in volume 2 of the Stratix II GX Device
DC & Switching Characteristics
Table 2–34
Selectable I/O Standards in Stratix II &
Selectable I/O Standards in Stratix II &
DC & Switching Characteristics
shows the list of output
DC & Switching
Altera Corporation
chapter in
S
October 2007
values of
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