EP2SGX30CF780C3N Altera, EP2SGX30CF780C3N Datasheet - Page 99
![IC STRATIX II GX 30K 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP2SGX30CF780C3N
Manufacturer Part Number
EP2SGX30CF780C3N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX30CF780C3N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
33880
# I/os (max)
361
Frequency (max)
816.9MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1926
EP2SGX30CF780C3N
EP2SGX30CF780C3N
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Figure 2–62. Regional Clocks
Altera Corporation
October 2007
CLK[3..0]
7
1
2
8
Dual-Regional Clock Network
A single source (CLK pin or PLL output) can generate a dual-regional
clock by driving two regional clock network lines in adjacent quadrants
(one from each quadrant), which allows logic that spans multiple
quadrants to utilize the same low skew clock. The routing of this clock
signal on an entire side has approximately the same speed but slightly
higher clock skew when compared with a clock signal that drives a single
quadrant. Internal logic-array routing can also drive a dual-regional
clock. Clock pins and enhanced PLL outputs on the top and bottom can
drive horizontal dual-regional clocks. Clock pins and fast PLL outputs on
the left and right can drive vertical dual-regional clocks, as shown in
Figure
RCLK
RCLK
[3..0]
[7..4]
2–63. Corner PLLs cannot drive dual-regional clocks.
[31..28]
[11..8]
RCLK
RCLK
CLK[15..12]
CLK[7..4]
11 5
12 6
[27..24]
[15..12]
RCLK
RCLK
Stratix II GX Device Handbook, Volume 1
[23..20]
[19..16]
RCLK
RCLK
Stratix II GX
Stratix II GX
Transceiver
Transceiver
Block
Block
Stratix II GX Architecture
2–91
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