EP2SGX30CF780C3N Altera, EP2SGX30CF780C3N Datasheet - Page 240
![IC STRATIX II GX 30K 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP2SGX30CF780C3N
Manufacturer Part Number
EP2SGX30CF780C3N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX30CF780C3N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
33880
# I/os (max)
361
Frequency (max)
816.9MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1926
EP2SGX30CF780C3N
EP2SGX30CF780C3N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Timing Model
4–70
Stratix II GX Device Handbook, Volume 1
(1)
(2)
t
t
t
t
t
t
t
t
t
t
t
PIN2COMBOUT_R
PIN2COMBOUT_C
COMBIN2PIN_R
COMBIN2PIN_C
CLR
PRE
CLKL
CLKH
SU
H
CO
Table 4–57. IOE Internal Timing Microparameters (Part 2 of 2)
Table 4–58. DSP Block Internal Timing Microparameters (Part 1 of 2)
Symbol
Symbol
This column refers to –3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
This column refers to –3 speed grades for EP2SGX130 devices.
Row input pin to IOE
combinational output
Column input pin to
IOE combinational
output
Row IOE data input to
combinational output
pin
Column IOE data input
to combinational output
pin
Minimum clear pulse
width
Minimum preset pulse
width
Minimum clock low
time
Minimum clock high
time
Input, pipeline, and
output register setup
time before clock
Input, pipeline, and
output register hold
time after clock
Input, pipeline, and
output register
clock-to-output
delay
Parameter
Parameter
Min
180
1101
Grade
-3 Speed
50
Min
410
428
991
200
200
600
600
0
Grade
-3 Speed
(1)
Max
Max
2026
1854
(1)
0
760
787
Min
189
52
1101
Grade
Min
-3 Speed
0
410
428
991
210
210
630
630
Grade
-3 Speed
(2)
Max
Max
2127
1946
(2)
0
798
825
Min
1101
200
Min
55
410
428
991
223
223
669
669
-4 Speed
0
-4 Speed
Grade
Grade
Max
2261
2069
Max
848
878
0
1101
Altera Corporation
Min
Min
241
410
428
991
268
268
804
804
67
-5 Speed
-5 Speed
0
Grade
Grade
1018
1054
2439
2246
Max
Max
June 2009
0
Unit
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
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