EP2SGX30CF780C3N Altera, EP2SGX30CF780C3N Datasheet - Page 44
![IC STRATIX II GX 30K 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP2SGX30CF780C3N
Manufacturer Part Number
EP2SGX30CF780C3N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX30CF780C3N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
33880
# I/os (max)
361
Frequency (max)
816.9MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1926
EP2SGX30CF780C3N
EP2SGX30CF780C3N
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Part Number
Manufacturer
Quantity
Price
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Transceivers
Figure 2–29. EP2SGX130 Device Inter-Transceiver and Global Clock Connections
Notes to
(1)
(2)
(3)
2–36
Stratix II GX Device Handbook, Volume 1
There are two transmitter PLLs in each transceiver block.
There are four receiver PLLs in each transceiver block.
The Global Clock line must be driven by an input pin.
Figure
2–29:
From Global
Clock Line (3)
16 Interface Clocks
To PLD
Global Clocks
IQ[4..0]
Global clk line
Global clk line
Global clk line
Global clk line
Global clk line
Global clk line
Global clk line
Global clk line
Global clk line
Global clk line
IQ[4..0]
IQ[4..0]
IQ[4..0]
IQ[4..0]
IQ[4..0]
To IQ0
IQ[4..0]
IQ[4..0]
To IQ1
IQ[4..0]
IQ[4..0]
To IQ4
IQ[4..0]
To IQ2
IQ[4..0]
IQ[4..0]
To IQ3
IQ[4..0]
IQ[4..0]
REFCLK0
REFCLK1
REFCLK0
REFCLK1
REFCLK0
REFCLK1
REFCLK0
REFCLK1
REFCLK0
REFCLK1
Transceiver Block 0
Transceiver Block 1
Transceiver Block 2
IQ[4..0]
Transceiver Block 3
Transceiver Block 4
÷2
÷2
÷2
÷2
÷2
÷2
÷2
÷2
÷2
÷2
From Global Clock Line (3)
From Global Clock Line (3)
From Global Clock Line (3)
From Global Clock Line (3)
From Global Clock Line (3)
Transceiver Clock Generator Block
Transceiver Clock Generator Block
Transceiver Clock Generator Block
Transceiver Clock Generator Block
Transceiver Clock Generator Block
Transmitter
Transmitter
Transmitter
Transmitter
Transmitter
PLL 1
PLL 1
PLL 1
PLL 1
PLL 1
Transmitter
Transmitter
PLL 0
Transmitter
PLL 0
Transmitter
Transmitter
PLL 0
PLL 0
PLL 0
Receiver
Receiver
Receiver
Receiver
Receiver
PLLs
PLLs
PLLs
PLLs
PLLs
4
4
4
4
4
Altera Corporation
October 2007
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