EP1S25F780C6 Altera, EP1S25F780C6 Datasheet - Page 232
![IC STRATIX FPGA 25K LE 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP1S25F780C6
Manufacturer Part Number
EP1S25F780C6
Description
IC STRATIX FPGA 25K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S25F780C6
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
25660
# I/os (max)
597
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
25660
Ram Bits
1944576
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1121
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S25F780C6
Manufacturer:
ALTERA
Quantity:
10
Company:
Part Number:
EP1S25F780C6
Manufacturer:
ALTERA
Quantity:
246
Part Number:
EP1S25F780C6
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP1S25F780C6ES
Manufacturer:
ALTERA
Quantity:
20 000
Company:
Part Number:
EP1S25F780C6N
Manufacturer:
ALTERA
Quantity:
1 045
Timing Model
4–62
Stratix Device Handbook, Volume 1
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
3.3-V LVCMOS
2.5-V LVCMOS
1.8-V LVCMOS
1.5-V LVCMOS
3.3-V GTL
2.5-V GTL
3.3-V GTL+
2.5-V GTL+
3.3-V SSTL-3 Class II
Table 4–101. Reporting Methodology For Maximum Timing For Single-Ended Output Pins (Part 1 of 2)
Notes
I/O Standard
(1), (2),
(3)
R
Figure 4–7. Output Delay Timing Reporting Setup Modeled by Quartus II
Notes to
(1)
(2)
Ω
–
–
–
–
–
–
–
–
–
–
–
–
–
UP
Output pin timing is reported at the output pin of the FPGA device. Additional
delays for loading and board trace delay need to be accounted for with IBIS model
simulations.
V
CCINT
R
Figure
Ω
–
–
–
–
–
–
–
–
–
–
–
–
–
DN
is 1.42-V unless otherwise specified.
4–7:
Loading and Termination
R
25
Ω
0
0
0
0
0
0
0
0
0
0
0
0
S
VCCIO
Output
Buffer
GND
25
25
25
25
25
R
Ω
–
–
–
–
–
–
–
–
T
Single-Ended Outputs
OUTPUT
2.950
2.370
1.650
1.400
2.950
2.370
1.650
1.400
2.950
2.370
2.950
2.370
2.950
V
(V)
CCIO
V
MEAS
VCCIO
GND
2.95
2.37
1.65
1.40
2.95
2.37
1.65
1.40
1.14
1.14
1.35
1.35
1.25
VTT
(V)
R
R
DN
UP
R
S
GND
V
TT
(pF)
C
R
10
10
10
10
10
10
10
10
30
30
30
30
30
C
L
T
L
Altera Corporation
Measurement
January 2006
V
1.500
1.200
0.880
0.750
1.500
1.200
0.880
0.750
0.740
0.740
0.880
0.880
1.250
Point
MEAS