EP1S25F780C6 Altera, EP1S25F780C6 Datasheet - Page 244
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EP1S25F780C6
Manufacturer Part Number
EP1S25F780C6
Description
IC STRATIX FPGA 25K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S25F780C6
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
25660
# I/os (max)
597
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
25660
Ram Bits
1944576
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1121
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S25F780C6
Manufacturer:
ALTERA
Quantity:
10
Company:
Part Number:
EP1S25F780C6
Manufacturer:
ALTERA
Quantity:
246
Part Number:
EP1S25F780C6
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP1S25F780C6ES
Manufacturer:
ALTERA
Quantity:
20 000
Company:
Part Number:
EP1S25F780C6N
Manufacturer:
ALTERA
Quantity:
1 045
Timing Model
4–74
Stratix Device Handbook, Volume 1
Note to
(1)
Decrease input delay
to internal cells
Decrease input delay
to input register
Decrease input delay
to output register
Increase delay to
output pin
Increase delay to
output enable pin
Increase output clock
enable delay
Increase input clock
enable delay
Increase output
enable clock enable
delay
Increase t
output pin
Table 4–110. Stratix IOE Programmable Delays on Row Pins
The delay chain delays vary for different device densities. These timing values only apply to EP1S30 and EP1S40
devices. Reference the timing information reported by the Quartus II software for other devices.
Parameter
Table 4–109
ZX
delay to
and
Off
Small
Medium
Large
On
Off
On
Off
On
Off
On
Off
On
Off
Small
Large
On
Off
Small
Large
On
Off
Small
Large
On
Off
On
Table
Setting
4–110:
-5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade
Min
3,970
3,390
2,810
3,900
1,240
1,016
1,016
1,993
Max
173
173
397
348
180
260
260
180
260
260
540
0
0
0
0
0
0
0
0
Min
4,367
3,729
3,091
4,290
1,364
1,118
1,118
2,092
Max
181
181
417
383
198
286
286
198
286
286
594
0
0
0
0
0
0
0
0
Note (1)
Min
5,022
4,288
3,554
4,933
1,568
1,285
1,285
2,092
Max
208
208
417
441
227
328
328
227
328
328
683
0
0
0
0
0
0
0
0
Min
Altera Corporation
January 2006
5,908
5,045
4,181
5,804
1,845
1,512
1,512
2,092
Max
245
245
417
518
267
386
386
267
386
386
804
0
0
0
0
0
0
0
0
Unit
ps
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