EP1S40F1020C5 Altera, EP1S40F1020C5 Datasheet - Page 25

• Manufacturer Part Number: EP1S40F1020C5
• Description: IC STRATIX FPGA 40K LE 1020-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40F1020C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 773
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 41250
• # I/os (max): 773
• Frequency (max): 500MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 41250
• Ram Bits: 3423744
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2089

Figure 2–7. LE in Dynamic Arithmetic Mode
Note to
(1)
Altera Corporation
July 2005
LAB Carry-In
Carry-In0
Carry-In1
The addnsub signal is tied to the carry input for the first LE of a carry chain only.
data1
data2
data3
(LAB Wide)
addnsub
Figure
(1)
2–7:
Carry-Out0
Carry-Select Chain
The carry-select chain provides a very fast carry-select function between
LEs in arithmetic mode. The carry-select chain uses the redundant carry
calculation to increase the speed of carry functions. The LE is configured
to calculate outputs for a possible carry-in of 1 and carry-in of 0 in
parallel. The carry-in0 and carry-in1 signals from a lower-order bit
feed forward into the higher-order bit via the parallel carry chain and feed
into both the LUT and the next portion of the carry chain. Carry-select
chains can begin in any LE within an LAB.
The speed advantage of the carry-select chain is in the parallel pre-
computation of carry chains. Since the LAB carry-in selects the
precomputed carry chain, not every LE is in the critical path. Only the
propagation delay between LAB carry-in generation (LE 5 and LE 10) are
now part of the critical path. This feature allows the Stratix architecture to
implement high-speed counters, adders, multipliers, parity functions,
and comparators of arbitrary width.
LUT
LUT
LUT
LUT
Carry-Out1
Register chain
connection
clock (LAB Wide)
(LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
sload
(LAB Wide)
Register Feedback
sclear
(LAB Wide)
Stratix Device Handbook, Volume 1
ADATA
ENA
D
ALD/PRE
aload
CLRN
Q
Stratix Architecture
Row, column, and
direct link routing
Row, column, and
direct link routing
Local routing
LUT chain
connection
Register
chain output
2–11