EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 19
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C2N
Manufacturer Part Number
EP3SL150F1152C2N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C2N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2409
EP3SL150F1152C2NES
EP3SL150F1152C2NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3SL150F1152C2N
Manufacturer:
ALTERA
Quantity:
20 000
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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Switching Characteristics
Table 1–22. TriMatrix Memory Block Performance Specifications for Stratix III Devices
© July 2010 Altera Corporation
M144K
(3),
M144K
(3),
Memory
Block
Type
(4)
(5)
True dual-port 16K × 9 or
8K × 18
True dual-port 4K × 36
Simple dual-port 16K × 9 or
8K × 18
Simple dual-port 4K × 36 or
2K × 72
ROM 1Port
ROM 2 Port
Single-port 16K × 9 or 8K × 18
Single-port 4K × 36
True dual-port 16K × 9, 8K × 18, or
4K × 36 with read-during-write
option set to Old Data
Simple dual-port 16K × 9,
8K × 18, 4K × 36, or 2K × 72 with
read-during-write option set to "Old
Data"
Simple dual-port 2K × 64 (with ECC)
Min Pulse Width (Clock High Time)
Min Pulse Width (Clock Low Time)
True dual-port 16K × 9 or
8K × 18
True dual-port 4K × 36
Simple dual-port 16K × 9 or
8K × 18
Simple dual-port 4K × 36 or
2K × 72
ROM 1Port
ROM 2 Port
Single-port 16K × 9 or 8K × 18
Single-port 4K × 36
True dual-port 16K × 9, 8K × 18, or
4K × 36 with read-during-write
option set to Old Data
Simple dual-port 16K × 9,
8K × 18, 4K × 36, or 2K × 72 with
read-during-write option set to Old
Data
Mode
ALUTs
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TriMatrix
Memory
—
—
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C2
1.1 V
V
350
520
350
565
580
545
385
580
325
350
255
800
500
425
520
425
565
580
545
475
580
325
350
CCL
(6)
=
V
1.1 V
1000
300
430
300
470
470
450
330
470
270
292
210
625
360
430
360
470
470
450
405
470
270
292
C3
CCL
=
V
1.1 V
1100
245
365
245
395
425
380
270
425
225
250
180
690
300
365
300
395
425
380
335
425
225
250
C4
CCL
(Note 1)
=
V
1.1 V
1100
Stratix III Device Handbook, Volume 2
245
365
245
395
425
380
270
425
225
250
180
690
300
365
300
395
425
380
335
425
225
250
CCL
=
C4L
(Part 2 of 3)
0.9 V
V
1800
1100
180
250
180
225
260
260
240
210
165
200
130
210
250
210
225
260
260
210
210
165
200
CCL
=
1.1 V
V
1000
280
405
280
440
470
425
310
470
255
275
195
625
340
405
340
440
470
425
380
470
255
275
I3
CCL
=
1.1 V
V
1100
245
365
245
395
425
380
270
425
225
250
180
690
300
365
300
395
425
380
335
425
225
250
I4
CCL
=
1–19
0.9 V
V
1800
1100
I4L
170
235
170
210
260
245
195
195
155
190
120
195
235
195
210
260
245
195
195
155
190
CCL
=
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
ps
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