EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 329

• Manufacturer Part Number: EP3SL150F1152C2N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C2N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2409; EP3SL150F1152C2NES

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Glossary
Table 1.
© July 2010 Altera Corporation
Glossary Table (Part 4 of 4)
Letter
W
V
X
Y
Z
V
V
V
V
V
V
V
Subject
D I F ( A C )
D I F ( D C )
C M ( D C )
V
V
I H ( A C )
I H ( D C )
I L ( A C )
I L ( D C )
V
V
V
V
O C M
—
—
—
I C M
W
O D
I D
I H
I L
DC Common Mode Input Voltage.
Input Common Mode Voltage: The common mode of the differential signal at the receiver.
Input Differential Voltage Swing: The difference in voltage between the positive and
complementary conductors of a differential transmission at the receiver.
AC Differential Input Voltage: Minimum AC input differential voltage required for switching.
DC Differential Input Voltage: Minimum DC input differential voltage required for switching.
Voltage Input High: The minimum positive voltage applied to the input that is accepted by the
device as a logic high.
High-level AC input voltage
High-level DC input voltage
Voltage Input Low: The maximum positive voltage applied to the input that is accepted by the
device as a logic low.
Low-level AC input voltage
Low-level DC input voltage
Output Common Mode Voltage: The common mode of the differential signal at the
transmitter.
Output differential Voltage Swing: The difference in voltage between the positive and
complementary conductors of a differential transmission at the transmitter.
High-Speed I/O Block: Clock Boost Factor
Definitions
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—
—
Stratix III Device Handbook, Volume 2
1–329