EP2S180F1020C4 Altera, EP2S180F1020C4 Datasheet - Page 109
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EP2S180F1020C4
Manufacturer Part Number
EP2S180F1020C4
Description
IC STRATIX II FPGA 180K 1020FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S180F1020C4
Number Of Logic Elements/cells
179400
Number Of Labs/clbs
8970
Total Ram Bits
9383040
Number Of I /o
742
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
179400
# I/os (max)
742
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
179400
Ram Bits
9383040
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
For Use With
544-1701 - DSP PRO KIT W/SII EP2S180N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1415
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S180F1020C4
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2S180F1020C4
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP2S180F1020C4N
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
EP2S180F1020C4N
Manufacturer:
ALTERA
Quantity:
748
Figure 2–59. Stratix II Receiver Channel
Altera Corporation
May 2007
Up to 1 Gbps
Eight Phase Clocks
+
–
refclk
f
data
Fast
PLL
8
retimed_data
DPA
An external pin or global or regional clock can drive the fast PLLs, which
can output up to three clocks: two multiplied high-speed clocks to drive
the SERDES block and/or external pin, and a low-speed clock to drive the
logic array. In addition, eight phase-shifted clocks from the VCO can feed
to the DPA circuitry.
For more information on the fast PLL, see the PLLs in Stratix II &
Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook
or the Stratix II GX Device Handbook.
The eight phase-shifted clocks from the fast PLL feed to the DPA block.
The DPA block selects the closest phase to the center of the serial data eye
to sample the incoming data. This allows the source-synchronous
circuitry to capture incoming data correctly regardless of the channel-to-
channel or clock-to-channel skew. The DPA block locks to a phase closest
to the serial data phase. The phase-aligned DPA clock is used to write the
data into the synchronizer.
The synchronizer sits between the DPA block and the data realignment
and SERDES circuitry. Since every channel utilizing the DPA block can
have a different phase selected to sample the data, the synchronizer is
needed to synchronize the data to the high-speed clock domain of the
data realignment and the SERDES circuitry.
DPA_clk
Synchronizer
diffioclk
load_en
D
Q
Data Realignment
Circuitry
Dedicated
Interface
Receiver
Stratix II Device Handbook, Volume 1
Stratix II Architecture
Data to R4, R24, C4, or
direct link interconnect
Regional or
global clock
10
2–101