EP2S180F1020C4 Altera, EP2S180F1020C4 Datasheet - Page 59
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EP2S180F1020C4
Manufacturer Part Number
EP2S180F1020C4
Description
IC STRATIX II FPGA 180K 1020FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S180F1020C4
Number Of Logic Elements/cells
179400
Number Of Labs/clbs
8970
Total Ram Bits
9383040
Number Of I /o
742
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
179400
# I/os (max)
742
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
179400
Ram Bits
9383040
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
For Use With
544-1701 - DSP PRO KIT W/SII EP2S180N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1415
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S180F1020C4
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2S180F1020C4
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP2S180F1020C4N
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
EP2S180F1020C4N
Manufacturer:
ALTERA
Quantity:
748
Figure 2–33. Dual-Regional Clocks
Figure 2–34. Hierarchical Clock Networks Per Quadrant
Altera Corporation
May 2007
PLLs
CLK[3..0]
Regional Clock Network [7..0]
Global Clock Network [15..0]
Clock Pins or PLL Clock Outputs
Can Drive Dual-Regional Network
CLK[7..4]
CLK[15..12]
Combined Resources
Within each quadrant, there are 24 distinct dedicated clocking resources
consisting of 16 global clock lines and eight regional clock lines.
Multiplexers are used with these clocks to form busses to drive LAB row
clocks, column IOE clocks, or row IOE clocks. Another multiplexer is
used at the LAB level to select three of the six row clocks to feed the ALM
registers in the LAB (see Figure 2–34).
CLK[11..8]
or Half-Quadrant
Clocks Available
to a Quadrant
Clock [23..0]
Clock Pins or PLL Clock
Outputs Can Drive
Dual-Regional Network
PLLs
CLK[3..0]
Stratix II Device Handbook, Volume 1
CLK[7..4]
CLK[15..12]
Stratix II Architecture
Column I/O Cell
IO_CLK[7..0]
Lab Row Clock [5..0]
Row I/O Cell
IO_CLK[7..0]
CLK[11..8]
2–51