XC5VSX50T-2FF665C Xilinx Inc, XC5VSX50T-2FF665C Datasheet - Page 22

IC FPGA VIRTEX-5 50K 665FCBGA

XC5VSX50T-2FF665C

Manufacturer Part Number
XC5VSX50T-2FF665C
Description
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr

Specifications of XC5VSX50T-2FF665C

Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
GTX_DUAL Tile Switching Characteristics
Consult UG198:Virtex-5 FPGA RocketIO GTX Transceiver User Guide for further information.
Table 42: GTX_DUAL Tile Performance
Table 43: Dynamic Reconfiguration Port (DRP) in the GTX_DUAL Tile Switching Characteristics
Table 44: GTX_DUAL Tile Reference Clock Switching Characteristics
X-Ref Target - Figure 10
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
3.
F
F
F
F
Symbol
GTXMAX
GPLLMAX
GPLLMIN
GTXDRPCLK
T
T
F
T
T
T
T
DCREF
PHASE
Symbol
GCLK
LOCK
Symbol
RCLK
FCLK
GJTT
GREFCLK can be used for serial bit rates up to 1 Gb/s; however, Jitter Specifications are not guaranteed when using GREFCLK.
GTX_DUAL jitter characteristics measured using a clock with specification T
with link margin trade off.
The selection of the reference clock is application dependent. This parameter describes the quality of the reference clock used during
transceiver jitter characterization - see
Reference clock frequency range
Reference clock rise time
Reference clock fall time
Reference clock duty cycle
Reference clock total jitter
Clock recovery frequency acquisition
time
Clock recovery phase acquisition time
GTX DCLK (DRP clock) maximum frequency
Maximum GTX transceiver data rate
Maximum PLL frequency
Minimum PLL frequency
80%
20%
Description
T
FCLK
(2, 3)
Figure 10: Reference Clock Timing Parameters
Table 46
(1)
Description
Description
and
Table
CLK
20% – 80%
80% – 20%
CLK
At 100 KHz
At 1 MHz
Initial PLL lock
Lock to data after PLL has
locked to the reference clock
T
47.
www.xilinx.com
RCLK
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Conditions
GJTT
. A reference clock with higher phase noise can be used
Min
60
40
3.25
1.48
200
6.5
-3
-3
ds202_05_100506
All Speed Grades
Speed Grade
Speed Grade
–145
–150
0.25
Typ
200
200
50
3.25
1.48
175
6.5
-2
-2
Max
650
200
60
4.25
3.25
1.48
1
150
-1
-1
dBc/Hz
dBc/Hz
Units
Units
Units
MHz
Gb/s
GHz
GHz
MHz
ms
ps
ps
µs
%
22

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