XC5VSX50T-2FF665C Xilinx Inc, XC5VSX50T-2FF665C Datasheet - Page 89

IC FPGA VIRTEX-5 50K 665FCBGA

XC5VSX50T-2FF665C

Manufacturer Part Number
XC5VSX50T-2FF665C
Description
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr

Specifications of XC5VSX50T-2FF665C

Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
DS202 (v5.3) May 5, 2010
Product Specification
06/26/07
07/26/07
09/27/07
11/05/07
12/11/07
02/05/08
Date
Version
3.3
3.4
3.5
3.6
3.7
3.8
• Added conditions to DV
• Changed the F
• Updated GTP maximum line rates to 3.75 Gb/s in
• Updated maximum frequencies in
• Added 3.75 Gb/s condition and changed maximum value of F
• Added 3.75 Gb/s sinusoidal jitter specification and changed maximum value of F
• Changed analog input common mode ranges in
• Changed T
• Added maximum value of I
• Revised
• In
• In
• Added Note 4 to T
• In
• Added I
• Added
• Removed unsupported XC5VSX95T -3 speed grade from
• Removed unsupported I/O standards (LVDS_33, LVDSEXT_33, and ULVDS_25) from
• Added values to
• In
• Removed note 1 from
• Revised DDR2 memory interface performance in
• Revised
• Removed XC5VSX95T -3 speed grade support from applicable tables.
• Removed unsupported I/O standard (LVPECL_33) from
• Added T
• Revised note 3 in
• Clarified notes in
• Revised note 1 in
• Added new devices (XC5VLX20T, XC5VLX155, and XC5VLX155T) throughout document.
• Removed -3 speed grade from XC5VSX95T device lists.
• Added
• Revised
• Revised Note 1 on
• Updated date on version 3.7. Other minor typographical edits.
• Updated the sentence: Xilinx does not specify the current or I/O behavior for other power-on sequences,
• Added values and notes to
• Revised T
• Revised R
• Revised -2 performance value for SPI-4.2 in
• Added T
• Split out the F
• Added
• Updated
• Revised Note 1 on
page
units for gain error and bipolar gain error.
updated LVDSEXT, 2.5V in
Table
Virtex-5 Device Pin-to-Pin Input Parameter Guidelines
revised Note 1 on
on
Combined I
devices in both tables.
Table 64, page
Table 70, page
Virtex-5 Device Pin-to-Pin Input Parameter
Virtex-5 Device Pin-to-Pin Input Parameter
page
18.
70.
DRP Clock Frequency
Table 31, page
Table
BATT
SMCO
IODDO_T
Table 54
Table 55
Virtex-5 Device Pin-to-Pin Output Parameter Guidelines
6.
Table 4
LLSKEW
XPPMTOL
PKGSKEW
VTTRXCQ
value and Note 2 to
75:
MAX
and T
GTXMAX
, T
Dynamic Reconfiguration Port (DRP) for DCM and PLL Before and After DCLK
PLL in PMCD Mode Switching Characteristics, page
and
Table 87
and changed the design software version in
44, added High Performance Mode to Note 2.
51, revised description of T
to add ISE 9.2i SP3 where applicable.
Table 76, page 57
Table
values in
DUTYCYCRANGE_200_400
Table 92
rows in
IODDO_IDATAIN
Table
Table 96
values and note 1 in
SMCKBY
values in
into I
Table 84
Table 52, page
16.
symbol name to F
PPIN
99.
99.
VTTRXQ
Table 71
to
REF
Table 27, page
www.xilinx.com
through
Table
Table 34, page
in
and
to
Table
and Note 4 to
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Table 99, page
to
Table 28, page
to
Table 70, page
, T
Table
Table
Table 98
Table 3, page
59.
values.
Table 33, page
90, and
IODDO_ODATAIN
and the F
Table
and
28. F
97.
3.
Table 35, page
Table 77, page
GTPMAX
97.
frequency range in
to match speed grade designations listed in
14. Removed I
MAX
17.
Table 94
Table
Table 53, page
Revision
SMDCCK
OUTMAX
Guidelines: Revised note 1 in
Guidelines: Revised note 1 in
84.
14.
51.
of clock is not an applicable limitation.
2.
Table 51, page
.
Table 53, page
17.
, and Note 3 to
Table 30, page
51. Revised the typical and maximum values and
to
/T
rows in
in
SMCCKD
Table
18.
Table 58
58.
Table 90
CCINTQ
Table 54
29.
97.
Table
GTX
Table 78, page
Table 55
.
26.
since it is included in
29.
in
Table 64, page
and added LVPECL_25.
16.
in
and
74, revised -2 value for smallest
and
Table 87
Table 34, page
56.
Table 92
for production devices.
Table
Table 91
Table 91
through
59.
55.
through
GRX
44.
17.
through
through
in
Table
Table 4, page
Table
Table
Table 35,
Table
90, and
51. Also
54.
Table
Table
97. Also
in
96.
97.
3.
89

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