XCV812E-6FG900C Xilinx Inc, XCV812E-6FG900C Datasheet - Page 14

• Manufacturer Part Number: XCV812E-6FG900C
• Description: IC FPGA 1.8V C-TEMP 900-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV812E-6FG900C

• Number Of Logic Elements/cells: 21168
• Number Of Labs/clbs: 4704
• Total Ram Bits: 1146880
• Number Of I /o: 556
• Number Of Gates: 254016
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 900-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 6:
Instruction Set
The Virtex-E Series boundary scan instruction set also
includes instructions to configure the device and read back
configuration data (CFG_IN, CFG_OUT, and JSTART). The
complete instruction set is coded as shown in
Data Registers
The primary data register is the boundary scan register. For
each IOB pin in the FPGA, bonded or not, it includes three
bits for In, Out, and 3-State Control. Non-IOB pins have
appropriate partial bit population if input-only or output-only.
Module 2 of 4
10
Boundary-Scan
USERCODE
RESERVED
Command
PRELOAD
CFG_OUT
SAMPLE/
EXTEST
IDCODE
BYPASS
CFG_IN
INTEST
JSTART
USER1
USER2
HIGHZ
Boundary Scan Instructions
Code (4:0)
All other
Binary
00000
00001
00010
00011
00100
00101
00111
01000
01001
01010
01100
11111
codes
Enable boundary-scan
EXTEST operation.
Enable boundary-scan
SAMPLE/PRELOAD
operation.
Access user-defined
register 1.
Access user-defined
register 2.
Access the
configuration bus for
read operations.
Access the
configuration bus for
write operations.
Enable boundary-scan
INTEST operation.
Enable shifting out
USER code.
Enable shifting out of ID
Code.
3-state output pins while
enabling the Bypass
Register.
Clock the start-up
sequence when
StartupClk is TCK.
Enable BYPASS.
Xilinx reserved
instructions.
Description
Table
6.
www.xilinx.com
1-800-255-7778
Each EXTEST CAPTURED-OR state captures all In, Out,
and 3-state pins.
The other standard data register is the single flip-flop
BYPASS register. It synchronizes data being passed
through the FPGA to the next downstream boundary scan
device.
The FPGA supports up to two additional internal scan
chains that can be specified using the BSCAN macro. The
macro provides two user pins (SEL1 and SEL2) which are
decodes of the USER1 and USER2 instructions respec-
tively. For these instructions, two corresponding pins (T
DO1 and TDO2) allow user scan data to be shifted out of
TDO.
Likewise, there are individual clock pins (DRCK1 and
DRCK2) for each user register. There is a common input pin
(TDI) and shared output pins that represent the state of the
TAP controller (RESET, SHIFT, and UPDATE).
Bit Sequence
The order within each IOB is: In, Out, 3-State. The
input-only pins contribute only the In bit to the boundary
scan I/O data register, while the output-only pins contributes
all three bits.
From a cavity-up view of the chip (as shown in EPIC), start-
ing in the upper right chip corner, the boundary scan
data-register bits are ordered as shown in
BSDL (Boundary Scan Description Language) files for Vir-
tex-E Series devices are available on the Xilinx web site in
the File Download area.
Figure 12: Boundary Scan Bit Sequence
Bit 0 ( TDO end)
Bit 1
Bit 2
(TDI end)
Right half of top-edge IOBs (Right to Left)
GCLK2
GCLK3
Left half of top-edge IOBs (Right to Left)
Left-edge IOBs (Top to Bottom)
M1
M0
M2
Left half of bottom-edge IOBs (Left to Right)
GCLK1
GCLK0
Right half of bottom-edge IOBs (Left to Right)
DONE
PROG
Right-edge IOBs (Bottom to Top)
CCLK
DS025-2 (v2.3) November 19, 2002
990602001
Figure
12.
R