XCV812E-6FG900C Xilinx Inc, XCV812E-6FG900C Datasheet - Page 33

• Manufacturer Part Number: XCV812E-6FG900C
• Description: IC FPGA 1.8V C-TEMP 900-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV812E-6FG900C

• Number Of Logic Elements/cells: 21168
• Number Of Labs/clbs: 4704
• Total Ram Bits: 1146880
• Number Of I /o: 556
• Number Of Gates: 254016
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 900-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Initialization
The block SelectRAM+ memory can initialize during the
device configuration sequence. The 16 initialization properties
of 64 hex values each (a total of 4096 bits) set the initialization
of each RAM. These properties appear in
ization properties not explicitly set configure as zeros. Partial
initialization strings pad with zeros. Initialization strings
greater than 64 hex values generate an error. The RAMs can
be simulated with the initialization values using generics in
VHDL simulators and parameters in Verilog simulators.
Initialization in VHDL and Synopsys
The block SelectRAM+ structures can be initialized in VHDL
for both simulation and synthesis for inclusion in the EDIF
output file. The simulation of the VHDL code uses a generic
to pass the initialization. Synopsys FPGA compiler does not
presently support generics. The initialization values instead
attach as attributes to the RAM by a built-in Synopsys
dc_script. The translate_off statement stops synthesis
translation of the generic statements. The following code
illustrates a module that employs these techniques.
Table 17:
Initialization in Verilog and Synopsys
The block SelectRAM+ structures can be initialized in Verilog
for both simulation and synthesis for inclusion in the EDIF
output file. The simulation of the Verilog code uses a def-
param to pass the initialization. The Synopsys FPGA com-
piler does not presently support defparam. The initialization
values instead attach as attributes to the RAM by a built-in
Synopsys dc_script. The translate_off statement stops syn-
thesis translation of the defparam statements. The following
code illustrates a module that employs these techniques.
DS025-2 (v2.3) November 19, 2002
Property
INIT_00
INIT_01
INIT_02
INIT_03
INIT_04
INIT_05
INIT_06
INIT_07
INIT_08
INIT_09
INIT_0a
INIT_0b
INIT_0c
INIT_0d
INIT_0e
INIT_0f
R
RAM Initialization Properties
Memory Cells
1279 to 1024
1535 to 1280
1791 to 2047
2047 to 1792
2303 to 2048
2559 to 2304
2815 to 2560
3071 to 2816
3327 to 3072
3583 to 3328
3839 to 3584
4095 to 3840
1023 to 768
511 to 256
767 to 512
Table
255 to 0
17. Any initial-
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
www.xilinx.com
1-800-255-7778
Design Examples
Creating a 32-bit Single-Port RAM
The true dual-read/write port functionality of the block
SelectRAM+ memory allows a single port, 128 deep by
32-bit wide RAM to be created using a single block
SelectRAM+ cell as shown
Interleaving the memory space, setting the LSB of the
address bus of Port A to 1 (V
address bus of Port B to 0 (GND), allows a 32-bit wide sin-
gle port RAM to be created.
Creating Two Single-Port RAMs
The true dual-read/write port functionality of the block
SelectRAM+ memory allows a single RAM to be split into two
single port memories of 2K bits each as shown in
In this example, a 512K x 4 RAM (Port A) and a 128 x 16
RAM (Port B) are created out of a single block SelectRAM+.
The address space for the RAM is split by fixing the MSB of
Port A to 1 (V
B to 0 (GND) for the lower 2K bits.
Block Memory Generation
The CoreGen program generates memory structures using
the block SelectRAM+ features. This program outputs
VHDL or Verilog simulation code templates and an EDIF file
for inclusion in a design.
ADDR[6:0], GND
GND, ADDR2[6:0]
Figure 36: 512 x 4 RAM and 128 x 16 RAM
ADDR[6:0], V
V
CC
, ADDR1[8:0]
Figure 35: Single Port 128 x 32 RAM
DI[31:16]
DI[15:0]
DI2[15:0]
DI1[3:0]
CC
RST2
CLK2
RST1
CLK1
WE2
RST
CLK
RST
CLK
WE1
EN2
WE
WE
EN1
EN
EN
CC
) for the upper 2K bits and the MSB of Port
WEA
ENA
RSTA
ADDRA[7:0]
DIA[15:0]
WEB
ENB
RSTB
ADDRB[7:0]
DIB[15:0]
CLKA
CLKB
WEA
ENA
RSTA
ADDRA[9:0]
DIA[3:0]
WEB
ENB
RSTB
ADDRB[7:0]
DIB[15:0]
CLKA
CLKB
RAMB4_S16_S16
RAMB4_S4_S16
inTable
CC
35.
DOA[15:0]
DOB[15:0]
DOA[3:0]
DOB[15:0]
), and the LSB of the
ds022_036_121399
ds022_037_121399
DO[31:16]
DO[15:0]
DO1[3:0]
DO2[15:0]
Module 2 of 4
Figure
36.
29