XCV812E-6FG900C Xilinx Inc, XCV812E-6FG900C Datasheet - Page 2

• Manufacturer Part Number: XCV812E-6FG900C
• Description: IC FPGA 1.8V C-TEMP 900-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV812E-6FG900C

• Number Of Logic Elements/cells: 21168
• Number Of Labs/clbs: 4704
• Total Ram Bits: 1146880
• Number Of I /o: 556
• Number Of Gates: 254016
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 900-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 1: Virtex-E Extended Memory Field-Programmable Gate Array Family Members
Virtex-E Compared to Virtex Devices
The Virtex-E family offers up to 43,200 logic cells in devices
up to 30% faster than the Virtex family.
I/O performance is increased to 622 Mb/s using Source
Synchronous data transmission architectures and synchro-
nous system performance up to 240 MHz using sin-
gled-ended SelectI/O technology. Additional I/O standards
are supported, notably LVPECL, LVDS, and BLVDS, which
use two pins per signal. Almost all signal pins can be used
for these new standards.
Virtex-E devices have up to 640 Kb of faster (250MHz)
block SelectRAM, but the individual RAMs are the same
size and structure as in the Virtex family. They also have
eight DLLs instead of the four in Virtex devices. Each indi-
vidual DLL is slightly improved with easier clock mirroring
and 4x frequency multiplication.
V
ory, is 1.8 V, instead of 2.5 V for Virtex devices. Advanced
processing and 0.18 µm design rules have resulted in
smaller dice, faster speed, and lower power consumption.
I/O pins are 3 V tolerant, and can be 5 V tolerant with an
external 100 Ω resistor. PCI 5 V is not supported. With the
addition of appropriate external resistors, any pin can toler-
ate any voltage desired.
Banking rules are different. With Virtex devices, all input
buffers are powered by V
LVTTL, LVCMOS2, and PCI input buffers are powered by
the I/O supply voltage V
The Virtex-E family is not bitstream-compatible with the Vir-
tex family, but Virtex designs can be compiled into equiva-
lent Virtex-E devices.
The same device in the same package for the Virtex-E and
Virtex families are pin-compatible with some minor excep-
tions. See the data sheet pinout section for details.
General Description
The Virtex-E FPGA family delivers high-performance,
high-capacity programmable logic solutions. Dramatic
increases in silicon efficiency result from optimizing the new
architecture for place-and-route efficiency and exploiting an
aggressive 6-layer metal 0.18 µm CMOS process. These
advances make Virtex-E FPGAs powerful and flexible alter-
Module 1 of 4
2
CCINT
XCV405E
XCV812E
Device
, the supply voltage for the internal logic and mem-
Logic Gates
129,600
254,016
CCO
CCINT
.
. With Virtex-E devices, the
CLB Array
40 x 60
56 x 84
10,800
21,168
Logic
Cells
www.xilinx.com
1-800-255-7778
Differential
natives to mask-programmed gate arrays. The Virtex-E fam-
ily includes the nine members in
Building on experience gained from Virtex FPGAs, the Vir-
tex-E family is an evolutionary step forward in programma-
ble logic design. Combining a wide variety of programmable
system features, a rich hierarchy of fast, flexible intercon-
nect resources, and advanced process technology, the Vir-
tex-E family delivers a high-speed and high-capacity
programmable logic solution that enhances design flexibility
while reducing time-to-market.
Virtex-E Architecture
Virtex-E devices feature a flexible, regular architecture that
comprises an array of configurable logic blocks (CLBs) sur-
rounded by programmable input/output blocks (IOBs), all
interconnected by a rich hierarchy of fast, versatile routing
resources. The abundance of routing resources permits the
Virtex-E family to accommodate even the largest and most
complex designs.
Virtex-E FPGAs are SRAM-based, and are customized by
loading configuration data into internal memory cells. Con-
figuration data can be read from an external SPROM (mas-
ter serial mode), or can be written into the FPGA
(SelectMAP™, slave serial, and JTAG modes).
The standard Xilinx Foundation Series™ and Alliance
Series™ Development systems deliver complete design
support for Virtex-E, covering every aspect from behavioral
and schematic entry, through simulation, automatic design
translation and implementation, to the creation and down-
loading of a configuration bit stream.
Higher Performance
Virtex-E devices provide better performance than previous
generations of FPGAs. Designs can achieve synchronous
system clock rates up to 240 MHz including I/O or 622 Mb/s
using Source Synchronous data transmission architech-
tures. Virtex-E I/Os comply fully with 3.3 V PCI specifica-
tions, and interfaces can be implemented that operate at
33 MHz or 66 MHz.
While performance is design-dependent, many designs
operate internally at speeds in excess of 133 MHz and can
achieve over 311 MHz.
mance data for representative circuits, using worst-case
timing parameters.
I/O Pairs
183
201
User I/O
404
556
Table 2, page
Production Product Specification
BlockRAM
1,146,880
573,440
Bits
DS025-1 (v1.5) July 17, 2002
Table
1.
3, shows perfor-
Distributed
RAM Bits
153,600
301,056
R