XC4020E-4HQ208I Xilinx Inc, XC4020E-4HQ208I Datasheet

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XC4020E-4HQ208I

Manufacturer Part Number
XC4020E-4HQ208I
Description
IC FPGA I-TEMP 5V 4SPD 208-HQFP
Manufacturer
Xilinx Inc
Series
XC4000E/Xr
Datasheet

Specifications of XC4020E-4HQ208I

Number Of Logic Elements/cells
1862
Number Of Labs/clbs
784
Total Ram Bits
25088
Number Of I /o
160
Number Of Gates
20000
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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May 14, 1999 (Version 1.6)
XC4000E and XC4000X Series
Features
Note: Information in this data sheet covers the XC4000E,
XC4000EX, and XC4000XL families. A separate data sheet
covers the XC4000XLA and XC4000XV families. Electrical
Specifications and package/pin information are covered in
separate sections for each family to make the information
easier to access, review, and print. For access to these sec-
tions, see the Xilinx web site at
http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp
• System featured Field-Programmable Gate Arrays
• System Performance beyond 80 MHz
• Flexible Array Architecture
• Low Power Segmented Routing Architecture
• Systems-Oriented Features
• Configured by Loading Binary File
• Read Back Capability
• Backward Compatible with XC4000 Devices
• Development System runs on most common computer
May 14, 1999 (Version 1.6)
- SelectRAM
- Fully PCI compliant (speed grades -2 and faster)
- Abundant flip-flops
- Flexible function generators
- Dedicated high-speed carry logic
- Wide edge decoders on each edge
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- Eight global low-skew clock or signal distribution
- IEEE 1149.1-compatible boundary scan logic
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- 12 mA sink current per XC4000E output
- Unlimited re-programmability
- Program verification
- Internal node observability
platforms
- Interfaces to popular design environments
- Fully automatic mapping, placement and routing
- Interactive design editor for design optimization
- synchronous write option
- dual-port RAM option
networks
support
TM
memory: on-chip ultra-fast RAM with
Product Obsolete or Under Obsolescence
R
0
0
0*
XC4000E and XC4000X Series Field
Programmable Gate Arrays
Product Specification
Low-Voltage Versions Available
• Low-Voltage Devices Function at 3.0 - 3.6 Volts
• XC4000XL: High Performance Low-Voltage Versions of
Additional XC4000X Series Features
• High Performance — 3.3 V XC4000XL
• High Capacity — Over 180,000 Usable Gates
• 5 V tolerant I/Os on XC4000XL
• 0.35 m SRAM process for XC4000XL
• Additional Routing Over XC4000E
• Buffered Interconnect for Maximum Speed Blocks
• Improved VersaRing
• 12 mA Sink Current Per XC4000X Output
• Flexible New High-Speed Clock Network
• Optional Multiplexer or 2-input Function Generator on
• Four Additional Address Bits in Master Parallel
Introduction
XC4000 Series high-performance, high-capacity Field Pro-
grammable Gate Arrays (FPGAs) provide the benefits of
custom CMOS VLSI, while avoiding the initial cost, long
development cycle, and inherent risk of a conventional
masked gate array.
The result of thirteen years of FPGA design experience and
feedback from thousands of customers, these FPGAs com-
bine architectural versatility, on-chip Select-RAM memory
with edge-triggered and dual-port modes, increased
speed, abundant routing resources, and new, sophisticated
software to achieve fully automated implementation of
complex, high-density, high-performance designs.
The XC4000E and XC4000X Series currently have 20
members, as shown in
XC4000EX devices
- almost twice the routing capacity for high-density
Pinout Flexibility
- Eight additional Early Buffers for shorter clock delays
- Virtually unlimited number of clock signals
Device Outputs
Configuration Mode
0
designs
Table
TM
I/O Interconnect for Better Fixed
1.
6-5
6

XC4020E-4HQ208I Summary of contents

Page 1

Product Obsolete or Under Obsolescence R May 14, 1999 (Version 1.6) XC4000E and XC4000X Series Features Note: Information in this data sheet covers the XC4000E, XC4000EX, and XC4000XL families. A separate data sheet covers the XC4000XLA and XC4000XV families. Electrical ...

Page 2

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000E and XC4000X Series Compared to the XC4000 For readers already familiar with the XC4000 family of Xil- inx Field Programmable Gate Arrays, the major new ...

Page 3

... XC4003E 238 3,000 XC4005E/XL 466 5,000 XC4006E 608 6,000 XC4008E 770 8,000 XC4010E/XL 950 10,000 XC4013E/XL 1368 13,000 XC4020E/XL 1862 20,000 XC4025E 2432 25,000 XC4028EX/XL 2432 28,000 XC4036EX/XL 3078 36,000 XC4044XL 3800 44,000 XC4052XL 4598 52,000 XC4062XL 5472 62,000 ...

Page 4

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays Input Thresholds The input thresholds of 5V devices can be globally config- ured for either TTL (1.2 V threshold) or CMOS (2.5 V threshold), just like XC2000 ...

Page 5

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays Detailed Functional Description XC4000 Series devices achieve high speed through advanced semiconductor technology and improved archi- tecture. The XC4000E and XC4000X support system clock rates of ...

Page 6

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays • • • LOGIC FUNCTION G1- LOGIC FUNCTION ...

Page 7

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays Set/Reset An asynchronous storage element input (SR) can be con- figured as either set or reset. This configuration option determines the state in which each flip-flop ...

Page 8

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays Supported CLB memory configurations and timing modes for single- and dual-port modes are shown in XC4000 Series devices are the first programmable logic devices with edge-triggered (synchronous) ...

Page 9

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays tions of the CLB, with the exception of the redefinition of the control signals. In 16x2 and 16x1 modes, the H’ function generator can be used ...

Page 10

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays • • • • • • • • • (CLOCK) Figure ...

Page 11

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays Dual-Port Edge-Triggered Mode In dual-port mode, both the F and G function generators are used to create a single 16x1 RAM array with one write port ...

Page 12

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays • • • • • • • • • ...

Page 13

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays • • • • • • • • • X6746 ...

Page 14

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays Fast Carry Logic Each CLB F and G function generator contains dedicated arithmetic logic for the fast generation of carry and borrow signals. This extra output is ...

Page 15

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays C C OUT IN DOWN CARRY LOGIC G CARRY OUT0 H1 F CARRY ...

Page 16

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays X2000 Figure 14: Detail of XC4000E Dedicated Carry Logic Input/Output Blocks (IOBs) User-configurable input/output blocks (IOBs) provide the ...

Page 17

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays T Out Output Clock Clock Enable Input Clock Figure 15: Simplified Block Diagram of XC4000E IOB T Out Output Clock I 1 ...

Page 18

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays Table 8: Supported Sources for XC4000 Series Device Inputs XC4000E/EX Series Inputs Source 5 V, TTL CMOS Any device, Vcc = 3.3 V, CMOS outputs Unreli XC4000 ...

Page 19

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays Additional Input Latch for Fast Capture (XC4000X only) The XC4000X IOB has an additional optional latch on the input. This latch, as shown in Figure 16, ...

Page 20

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays Any XC4000 Series 5-Volt device with its outputs config- ured in TTL mode can drive the inputs of any typical 3.3-Volt device. (For a detailed discussion of ...

Page 21

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays Output Multiplexer/2-Input Function Generator (XC4000X only) As shown in Figure 16 on page 21, the output path in the XC4000X IOB contains an additional multiplexer not ...

Page 22

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays or clear on reset and after configuration. Other than the glo- bal GSR net, no user-controlled set/reset signal is available to the I/O flip-flops. The choice of ...

Page 23

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays ~100 k "Weak Keeper" Figure 22: 3-State Buffers Implement a Multiplexer Wide Edge Decoders Dedicated decoder circuitry boosts the performance of wide decoding functions. When the ...

Page 24

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays The oscillator output is optionally available after configura- tion. Any two of four resynchronized taps of a built-in divider are also available. These taps are at the ...

Page 25

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays Quad Long Global Clock Figure 25: High-Level Routing Diagram of XC4000 Series CLB (shaded arrows indicate XC4000X only) Table 14: Routing per CLB in XC4000 Series ...

Page 26

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays Common to XC4000E and XC4000X XC4000X only Programmable Switch Matrix Figure 27: Detail of Programmable Interconnect Associated with XC4000 Series CLB 6-30 R QUAD DOUBLE SINGLE DOUBLE ...

Page 27

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays CLB CLB PSM PSM CLB CLB PSM PSM CLB CLB Figure 28: Single- and Double-Length Lines, with Programmable Switch Matrices (PSMs) Double-Length Lines The double-length lines ...

Page 28

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays circuit prevents undefined floating levels. However overridden by any driver, even a pull-up resistor. Each XC4000E longline has a programmable splitter switch at its center, ...

Page 29

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays WED IOB WED IOB WED Direct Connect Figure 31: High-Level Routing Diagram of XC4000 Series VersaRing (Left Edge) WED = Wide Edge Decoder, IOB = I/O ...

Page 30

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays Common to XC4000E and XC4000X XC4000X only Figure 33: Detail of Programmable Interconnect Associated with XC4000 Series IOB (Left Edge) 6-34 IOB ...

Page 31

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays IOB inputs and outputs interface with the octal lines via the single-length interconnect lines. Single-length lines are also used for communication between the octals and dou- ...

Page 32

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays BUFGS PGCK1 SGCK1 BUFGP 4 IOB locals Any BUFGS X4 locals One BUFGP per Global Line IOB BUFGS PGCK2 SGCK2 BUFGP Figure 34: XC4000E Global Net Distribution ...

Page 33

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays Global Nets and Buffers (XC4000X only) Eight vertical longlines in each CLB column are driven by special global buffers. These longlines are in addition to the ...

Page 34

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays 8 IOB IOB 1 I CLB CLB CLB CLB IOB IOB 3 Figure 36: Any BUFGLS (GCK1 - GCK8) Can Drive ...

Page 35

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays The top and bottom Global Early buffers are about 1 ns slower clock to out than the left and right Global Early buff- ers. The Global ...

Page 36

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays Table 16: Pin Descriptions I/O I/O During After Pin Name Config. Config. Permanently Dedicated Pins Eight or more (depending on package) connections to the nominal +5 V ...

Page 37

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays Table 16: Pin Descriptions (Continued) I/O I/O During After Pin Name Config. Config. If boundary scan is used, these pins are Test Data In, Test Clock, ...

Page 38

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays Table 16: Pin Descriptions (Continued) I/O I/O During After Pin Name Config. Config. These four inputs are used in Asynchronous Peripheral mode. The chip is selected when ...

Page 39

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays Figure 41 on page diagram of the XC4000 Series boundary scan logic. It includes three bits of Data Register per IOB, the IEEE ...

Page 40

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB BYPASS REGISTER INSTRUCTION REGISTER TDI Figure 41: XC4000 Series Boundary Scan Logic Instruction Set The XC4000 ...

Page 41

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays Table 17: Boundary Scan Instructions Instruction I2 Test TDO Source I1 I0 Selected EXTEST SAMPLE/PR DR ELOAD 0 1 ...

Page 42

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays Configuration Modes XC4000E devices have six configuration modes. XC4000X devices have the same six modes, plus an additional con- figuration mode. These modes are selected by a ...

Page 43

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays is passed through and is captured by each FPGA when it recognizes the 0010 preamble. Following the length-count data, each FPGA outputs a High on DOUT ...

Page 44

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays Setting CCLK Frequency For Master modes, CCLK can be generated in either of two frequencies. In the default slow mode, the frequency ranges from 0.5 MHz to ...

Page 45

... A change in the checksum indi- cates a change in the Readback bitstream. A comparison to a previous checksum is meaningful only if the readback data is independent of the current device state. CLB out- 19 frame data puts should not be included (Read Capture option not XC4013E XC4020E XC4025E 13,000 20,000 25,000 576 784 ...

Page 46

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays used), and if RAM is present, the RAM content must be unchanged. Statistically, one error out of 2048 might go undetected. Configuration Sequence There are four major ...

Page 47

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays Low. During this time delay long as the PROGRAM input is asserted, the configuration logic is held in a Config- uration Memory Clear state. ...

Page 48

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays The default option, and the most practical one, is for DONE to go High first, disconnecting the configuration data source and avoiding any contention when the I/Os ...

Page 49

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays Length Count Match CCLK DONE I/O XC2000 Global Reset DONE XC3000 I/O Global Reset DONE I/O XC4000E/X CCLK_NOSYNC GSR Active DONE IN DONE C1 ...

Page 50

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays Start-up from a User Clock (STARTUP.CLK) When, instead of CCLK, a user-supplied start-up clock is selected used to bridge the unknown phase relation- ship between ...

Page 51

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays Q3 Q1/Q4 STARTUP DONE FULL LENGTH COUNT K CLEAR MEMORY CCLK ...

Page 52

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays IF UNCONNECTED, DEFAULT IS CCLK READ_TRIGGER MD0 Figure 49: Readback Schematic Example Readback Options Readback options are: Read Capture, Read Abort, and Clock Select. They are set ...

Page 53

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000E/EX/XL Program Readback Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal ...

Page 54

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays Table 22: Pin Functions During Configuration CONFIGURATION MODE <M2:M1:M0> SLAVE MASTER SERIAL SERIAL PERIPHERAL <1:1:1> <0:0:0> M2(HIGH) (I) M2(LOW) (I) M2(LOW) (I) M1(HIGH) (I) M1(LOW) (I) M1(HIGH) ...

Page 55

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays Table 23: Pin Functions During Configuration CONFIGURATION MODE <M2:M1:M0> SLAVE MASTER SYNCH. SERIAL SERIAL PERIPHERAL <1:1:1> <0:0:0> <0:1:1> M2(HIGH) (I) M2(LOW) (I) M2(LOW) (I) M1(HIGH) (I) ...

Page 56

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays Configuration Timing The seven configuration modes are discussed in detail in this section. Timing specifications are included. Slave Serial Mode In Slave Serial mode, an external signal ...

Page 57

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays Master Serial Mode In Master Serial mode, the CCLK output of the lead FPGA drives a Xilinx Serial PROM that feeds the FPGA DIN input. Each ...

Page 58

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays Master Parallel Modes In the two Master Parallel modes, the lead FPGA directly addresses an industry-standard byte-wide EPROM, and accepts eight data bits just before incrementing or ...

Page 59

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays A0-A17 (output) D0-D7 RCLK (output) CCLK (output) DOUT (output) Description Delay to Address valid RCLK Data setup time Data hold time Notes power-up, Vcc ...

Page 60

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays Synchronous Peripheral Mode Synchronous Peripheral mode can also be considered Slave Parallel mode. An external signal drives the CCLK input(s) of the FPGA(s). The first byte of ...

Page 61

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays CCLK INIT BYTE 0 DOUT RDY/BUSY Description INIT (High) setup time setup time hold time CCLK CCLK High time CCLK ...

Page 62

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays Asynchronous Peripheral Mode Write to FPGA Asynchronous Peripheral mode uses the trailing edge of the logic AND condition of WS and CS0 being Low and RS and ...

Page 63

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays Write to LCA WS/CS0 RS, CS1 D0-D7 CCLK 4 T WTRB RDY/BUSY DOUT Description Effective Write time (CS0, WS=Low; RS, ...

Page 64

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays Configuration Switching Characteristics T Vcc PROGRAM INIT CCLK OUTPUT or INPUT X1532 Master Modes (XC4000E/EX) Description Power-On Reset Program Latency CCLK (output) Delay CCLK (output) Period, slow ...

Page 65

Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays Product Availability Table 24, Table 25, and Table 26 show the planned packages and speed grades for XC4000-Series devices. Call your local sales office for the ...

Page 66

... XC4005E - XC4006E - XC4008E - XC4010E - XC4013E - XC4020E - XC4025E -3 -2 1/29/ Commercial + Industrial +100 C J Table 26: Component Availability Chart for XC4000EX FPGAs PINS 208 High-Perf. TYPE QFP HQ208 HQ240 CODE - XC4028EX - XC4036EX -3 -2 1/29/ Commercial + Industrial +100 C J 6-70 120 144 156 160 ...

Page 67

... XC4005E 112 61 77 XC4006E 128 61 XC4008E 144 61 XC4010E 160 61 XC4013E 192 XC4020E 224 XC4025E 256 1/29/99 Table 29: User I/O Chart for XC4000EX FPGAs Max Device I/O HQ208 HQ240 XC4028EX 256 160 XC4036EX 288 1/29/99 May 14, 1999 (Version 1.6) Maximum User Accessible I/O by Package Type ...

Page 68

Product Obsolete or Under Obsolescence XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000 Series Electrical Characteristics and Device-Specific Pinout Table For the latest Electrical Characteristics and package/pinout information for each XC4000 Family, see the Xilinx web site at http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp ...

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