XC4020E-4HQ208I Xilinx Inc, XC4020E-4HQ208I Datasheet - Page 28

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XC4020E-4HQ208I

Manufacturer Part Number
XC4020E-4HQ208I
Description
IC FPGA I-TEMP 5V 4SPD 208-HQFP
Manufacturer
Xilinx Inc
Series
XC4000E/Xr
Datasheet

Specifications of XC4020E-4HQ208I

Number Of Logic Elements/cells
1862
Number Of Labs/clbs
784
Total Ram Bits
25088
Number Of I /o
160
Number Of Gates
20000
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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XC4000E and XC4000X Series Field Programmable Gate Arrays
circuit prevents undefined floating levels. However, it is
overridden by any driver, even a pull-up resistor.
Each XC4000E longline has a programmable splitter switch
at its center, as does each XC4000X longline driven by
TBUFs. This switch can separate the line into two indepen-
dent routing channels, each running half the width or height
of the array.
Each XC4000X longline not driven by TBUFs has a buff-
ered programmable splitter switch at the 1/4, 1/2, and 3/4
points of the array. Due to the buffering, XC4000X longline
performance does not deteriorate with the larger array
sizes. If the longline is split, the resulting partial longlines
are independent.
Routing connectivity of the longlines is shown in
on page
Direct Interconnect (XC4000X only)
The XC4000X offers two direct, efficient and fast connec-
tions between adjacent CLBs. These nets facilitate a data
flow from the left to the right side of the device, or from the
top to the bottom, as shown in
the direct interconnect exhibit minimum interconnect prop-
agation delay and use no general routing resources.
The direct interconnect is also present between CLBs and
adjacent IOBs. Each IOB on the left and top device edges
has a direct path to the nearest CLB. Each CLB on the right
and bottom edges of the array has a direct path to the near-
est two IOBs, since there are two IOBs for each row or col-
umn of CLBs.
The place and route software uses direct interconnect
whenever possible, to maximize routing resources and min-
imize interconnect delays.
6-32
Figure 30: XC4000X Direct Interconnect
IOB
IOB
IOB
IOB
30.
~ ~
CLB
CLB
~ ~
Product Obsolete or Under Obsolescence
~ ~
CLB
CLB
Figure
~ ~
30. Signals routed on
~ ~
CLB
CLB
~ ~
Figure 27
IOB
IOB
IOB
IOB
X6603
I/O Routing
XC4000 Series devices have additional routing around the
IOB ring. This routing is called a VersaRing. The VersaRing
facilitates pin-swapping and redesign without affecting
board layout. Included are eight double-length lines span-
ning two CLBs (four IOBs), and four longlines. Global lines
and Wide Edge Decoder lines are provided. XC4000X
devices also include eight octal lines.
A high-level diagram of the VersaRing is shown in
Figure
only in XC4000X devices.
Figure 33 on page 34
and XC4000X VersaRing. The area shown includes two
IOBs. There are two IOBs per CLB row or column, there-
fore this diagram corresponds to the CLB routing diagram
shown in
sent routing and routing connections present only in
XC4000X devices.
Octal I/O Routing (XC4000X only)
Between the XC4000X CLB array and the pad ring, eight
interconnect tracks provide for versatility in pin assignment
and fixed pinout flexibility. (See
These routing tracks are called octals, because they can be
broken every eight CLBs (sixteen IOBs) by a programma-
ble buffer that also functions as a splitter switch. The buffers
are staggered, so each line goes through a buffer at every
eighth CLB location around the device edge.
The octal lines bend around the corners of the device. The
lines cross at the corners in such a way that the segment
most recently buffered before the turn has the farthest dis-
tance to travel before the next buffer, as shown in
Figure
32.
31. The shaded arrows represent routing present
Figure 27 on page
is a detailed diagram of the XC4000E
30. The shaded areas repre-
Figure 32 on page
May 14, 1999 (Version 1.6)
33.)
R

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