XC4020E-4HQ208I Xilinx Inc, XC4020E-4HQ208I Datasheet - Page 24

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XC4020E-4HQ208I

Manufacturer Part Number
XC4020E-4HQ208I
Description
IC FPGA I-TEMP 5V 4SPD 208-HQFP
Manufacturer
Xilinx Inc
Series
XC4000E/Xr
Datasheet

Specifications of XC4020E-4HQ208I

Number Of Logic Elements/cells
1862
Number Of Labs/clbs
784
Total Ram Bits
25088
Number Of I /o
160
Number Of Gates
20000
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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XC4000E and XC4000X Series Field Programmable Gate Arrays
The oscillator output is optionally available after configura-
tion. Any two of four resynchronized taps of a built-in divider
are also available. These taps are at the fourth, ninth, four-
teenth and nineteenth bits of the divider. Therefore, if the
primary oscillator output is running at the nominal 8 MHz,
the user has access to an 8 MHz clock, plus any two of 500
kHz, 16kHz, 490Hz and 15Hz (up to 10% lower for low-volt-
age devices). These frequencies can vary by as much as
-50% or +25%.
These signals can be accessed by placing the OSC4
library element in a schematic or in HDL code (see
Figure
The oscillator is automatically disabled after configuration if
the OSC4 symbol is not used in the design.
Programmable Interconnect
All internal connections are composed of metal segments
with programmable switching points and switching matrices
to implement the desired routing. A structured, hierarchical
matrix of routing resources is provided to achieve efficient
automated routing.
The XC4000E and XC4000X share a basic interconnect
structure. XC4000X devices, however, have additional rout-
ing not available in the XC4000E. The extra routing
resources allow high utilization in high-capacity devices. All
XC4000X-specific routing resources are clearly identified
throughout this section. Any resources not identified as
XC4000X-specific are present in all XC4000 Series
devices.
This section describes the varied routing resources avail-
able in XC4000 Series devices. The implementation soft-
ware automatically assigns the appropriate resources
based on the density and timing requirements of the
design.
Interconnect Overview
There are several types of interconnect.
• CLB routing is associated with each row and column of
• IOB routing forms a ring (called a VersaRing) around
6-28
the CLB array.
the outside of the CLB array. It connects the I/O with the
internal logic blocks.
24).
Product Obsolete or Under Obsolescence
• Global routing consists of dedicated networks primarily
Five interconnect types are distinguished by the relative
length of their segments: single-length lines, double-length
lines, quad and octal lines (XC4000X only), and longlines.
In the XC4000X, direct connects allow fast data flow
between adjacent CLBs, and between IOBs and CLBs.
Extra routing is included in the IOB pad ring. The XC4000X
also includes a ring of octal interconnect lines near the
IOBs to improve pin-swapping and routing to locked pins.
XC4000E/X devices include two types of global buffers.
These global buffers have different properties, and are
intended for different purposes. They are discussed in
detail later in this section.
CLB Routing Connections
A high-level diagram of the routing resources associated
with one CLB is shown in
represent routing present only in XC4000X devices.
Table 14
in XC4000E and XC4000X CLB arrays. Clearly, very large
designs, or designs with a great deal of interconnect, will
route more easily in the XC4000X. Smaller XC4000E
designs, typically requiring significantly less interconnect,
do not require the additional routing.
Figure 27 on page 30
XC4000E and the XC4000X CLB, with associated routing.
The shaded square is the programmable switch matrix,
present in both the XC4000E and the XC4000X. The
L-shaped shaded area is present only in XC4000X devices.
As shown in the figure, the XC4000X block is essentially an
XC4000E block with additional routing.
CLB inputs and outputs are distributed on all four sides,
providing maximum routing flexibility. In general, the entire
architecture is symmetrical and regular. It is well suited to
established placement and routing algorithms. Inputs, out-
puts, and function generators can freely swap positions
within a CLB to avoid routing congestion during the place-
ment and routing operation.
designed to distribute clocks throughout the device with
minimum delay and skew. Global routing can also be
used for other high-fanout signals.
shows how much routing of each type is available
is a detailed diagram of both the
Figure
May 14, 1999 (Version 1.6)
25. The shaded arrows
R

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