20-101-1094 Rabbit Semiconductor, 20-101-1094 Datasheet - Page 99
![MCU RCM4000 RABBITCORE](/photos/6/74/67480/20-101-1094_sml.jpg)
20-101-1094
Manufacturer Part Number
20-101-1094
Description
MCU RCM4000 RABBITCORE
Manufacturer
Rabbit Semiconductor
Datasheet
1.20-101-1094.pdf
(130 pages)
Specifications of 20-101-1094
Module/board Type
MPU Core Module
Product
Microcontroller Modules
Core Processor
Rabbit 4000
Clock Speed
58.98 MHz
Interface Type
Ethernet, Serial
Flash
512 KB
Timers
10 x 8 bit, 1 x 10 bit, 1 x 16 bit
Operating Supply Voltage
3 V to 3.6 V
Board Size
47 mm x 61 mm x 20 mm
Core
RCM4000
Processor Series
RCM4000
Cpu Core
Rabbit 4000
For Use With/related Products
RCM4000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
316-1139
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Table A-8 lists the delays in gross memory access time for several values of VDD
The measurements are taken at the 50% points under the following conditions.
• T = -40°C to 85°C, V = VDD
• Internal clock to nonloaded CLK pin delay 1 ns @ 85°C/3.0 V
The clock to address output delays are similar, and apply to the following delays.
• T
• T
• T
• T
• T
• T
The data setup time delays are similar for both T
When the spectrum spreader is enabled with the clock doubler, every other clock cycle is
shortened (sometimes lengthened) by a maximum amount given in the table above. The
shortening takes place by shortening the high part of the clock. If the doubler is not
enabled, then every clock is shortened during the low part of the clock period. The maxi-
mum shortening for a pair of clocks combined is shown in the table.
Rabbit’s Technical Note TN227, Interfacing External I/O with Rabbit Microprocessor
Designs, contains suggestions for interfacing I/O devices to the Rabbit 4000 microproces-
sors.
User’s Manual
VDD
(V)
adr
3.3
1.8
CSx
IOCSx
IORD
IOWR
BUFEN
, the clock to address delay
IO
, the clock to memory chip select delay
, the clock to I/O read strobe delay
, the clock to I/O write strobe delay
, the clock to I/O chip select delay
, the clock to I/O buffer enable delay
30 pF 60 pF 90 pF
Clock to Address
18
6
Output Delay
Table A-8. Preliminary Data and Clock Delays
(ns)
24
8
11
33
IO
Data Setup
Time Delay
±10%
(ns)
1
3
0.5 ns setting
setup
no dbl / dbl
2.3 / 2.3
7 / 6.5
and T
Spectrum Spreader Delay
hold
.
Worst-Case
1 ns setting
no dbl / dbl
3 / 4.5
8 / 12
(ns)
2 ns setting
no dbl / dbl
11 / 22
4.5 / 9
IO
.
93
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