MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 195

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

MOTOROLA
Chapter 9
SDRAM Controller
This chapter describes configuration and operation of the synchronous DRAM controller
component of the SIM including a general description of signals involved in SDRAM
operations. It provides interface information for memory configurations using most
common SDRAM devices for both 16- and 32-bit wide data buses. The chapter concludes
with signal timing diagrams.
9.1 Overview
The MCF5272 incorporates an SDRAM controller, whose main features are as follows:
9.2 SDRAM Controller Signals
The SDRAM controller provides all required signals for glueless interfacing to a variety of
JEDEC-compliant SDRAM devices. RAS/CAS address multiplexing and the SDRAM pin
A10 auto-precharge function is software configurable for different page sizes. To maintain
refresh capability without conflicting with concurrent accesses on the address and data
buses, RAS0, CAS0, SDWE, SDBA[0:1], SDCLKE, A10_PRECHG, and the SDRAM
bank selects are dedicated SDRAM signals.
• Glueless interface to a variety of JEDEC-compliant SDRAM devices.
• MCF5272 data bus width of 16 or 32 bits to SDRAM memory array
• 16- to 256-Mbit device support
• Dedicated bank address pins to provide pin out compatibility for different SDRAM
• Page size from 256–1024 column address locations
• 6-1-1-1 timing for burst-read; 3-1-1-1 timing for burst-write accesses (assuming a
• CAS latencies of 1 and 2
• Up to four concurrently activated banks
• SDRAM power down and self refresh
• Refresh timer prescaler supports system clock down to 5 MHz maintaining a
• Auto initialization of SDRAM
sizes with a single printed circuit board layout
page hit at 66 MHz)
15.6-µS refresh cycle
Chapter 9. SDRAM Controller
9-1