CY7C63231A-PXC Cypress Semiconductor Corp, CY7C63231A-PXC Datasheet
CY7C63231A-PXC
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CY7C63231A-PXC Summary of contents
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... CPU clock ❐ Internal memory ❐ 96 bytes of RAM ❐ 3 Kbytes of EPROM ❐ Cypress Semiconductor Corporation Document #: 38-08028 Rev. *D enCoRe™ USB Low-Speed USB Interface can auto-configure to operate as PS/2 or USB ❐ No external components for switching between PS/2 and ❐ USB modes I/O ports ■ ...
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Functional Overview enCoRe USB - The New USB Standard Cypress has reinvented its leadership position in the low-speed USB market with a new family of innovative microcontrollers. Introducing...enCoRe™ USB—“enhanced Component Reduction.” Cypress has leveraged its design expertise in USB solutions ...
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Logic Block Diagram XTALIN/P2.1 XTALOUT/P2.2 XTALIN/P2.1 Internal Oscillator EPROM 3 Kbytes Brown-Out Reset W atch Dog Timer Low Voltage Reset Document #: 38-08028 Rev. *D XTALOUT Xtal W ake-Up RAM Oscillator Timer 96 Bytes 8-bit RISC Core Interrupt USB Controller ...
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Contents Pin Configurations ........................................................... 5 Pin Assignments .............................................................. 6 Programming Model ......................................................... 7 Program Counter (PC) ................................................ 7 8-bit Accumulator (A) ................................................... 7 8-bit Index Register (X) ............................................... 7 8-bit Program Stack Pointer (PSP) .............................. 7 8-bit Data Stack Pointer ...
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... Pin Configurations CY7C63221A 16-pin PDIP P0 P0.5 P0.6 P0 P0 D+/SCLK D–/SDATA PP 10 VREG/P2 XTALOUT/P2.2 XTALIN/P2.1 8 Document #: 38-08028 Rev. *D (Top View) CY7C63231A 18-pin SOIC/PDIP P0.4 P0 P0.1 2 P0.5 P0.6 P0 P0 P1.1 P1 D+/SCLK D–/SDATA VREG/P2.0 CC XTALIN/P2.1 10 XTALOUT/P2.2 9 CY7C63221/31A ...
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... VREG/P2 Document #: 38-08028 Rev. *D CY7C63231A/ CY7C63221A-XC 18-Pin/Pad USB differential data lines (D– and D+), or PS/2 clock and data 12 13 signals (SDATA and SCLK GPIO Port 0 capable of sinking mA/pin, or sinking 15, 16, 17, 18 controlled low or high programmable current. Can also source 2 mA current, provide a resistive pull-up, or serve as a high-impedance input ...
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Programming Model Refer to the CYASM Assembler User’s Guide for more details on firmware operation with the microcontrollers. Program Counter (PC) The 14-bit program counter (PC) allows access for 3 Kbytes of EPROM using the architecture. The program counter is ...
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Address Modes The microcontroller supports three addressing modes for instructions that require data operands: data, direct, and indexed. Data The “Data” address mode refers to a data operand that is actually a constant encoded in the instruction example, ...
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Instruction Set Summary Refer to the CYASM Assembler User’s Guide for detailed information on these instructions. Note that conditional jump instructions (i.e. JC, JNC, JZ, JNZ) take 5 cycles if jump is taken, 4 cycles if no jump. MNEMONIC Operand ...
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Memory Organization Program Memory Organization Figure 1. Program Memory Space with Interrupt Vector Table After reset 14-bit PC Note 1. The upper 32 bytes of the 3K PROM are reserved. Therefore, user’s program must not over-write this space. Document #: ...
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Data Memory Organization The microcontroller provides 96 bytes of data RAM. In normal usage, the SRAM is partitioned into four areas: program stack, data stack, user variables and USB endpoint FIFOs as shown below: After reset 8-bit DSP 8-bit PSP ...
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I/O Register Summary I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads the selected port into the accumulator. IOWR writes data from the accumulator to the selected port. Indexed I/O Write (IOWX) ...
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Clocking The chip can be clocked from either the internal on-chip clock, or from an oscillator based on an external resonator/crystal, as shown in Figure 2. No additional capacitance is included on chip at the XTALIN/OUT pins. Operation is controlled ...
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Bit 3: Low-voltage Reset Disable When V drops below V (see Section for the value of CC LVR V ) and the Low-voltage Reset circuit is enabled, the micro- LVR controller enters a partial suspend state for a period of ...
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LVR/BOR and WDR respectively. The firmware can interrogate these bits to determine the cause of a reset. The microcontroller begins execution from ROM address 0x0000 after a LVR, BOR, or WDR reset. Although this looks like ...
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Suspend Mode The parts support a versatile low-power suspend mode. In suspend mode, only an enabled interrupt or a LOW state on the D–/SDATA pin will wake the part. Two options are available. For lowest power, all internal circuits can ...
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Table 2. Wake-up Timer Adjust Settings Adjust Bits [2:0] (Bits [6:4] in Figure 3) 000 (reset state) 001 010 011 100 101 110 111 See Section for the value of t General Purpose I/O Ports Ports 0 and 1 provide ...
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Bit # 7 6 Bit Name Read/Write R/W R/W Reset 0 0 Bit [7:0]: P0[7: Port Pin is logic HIGH Bit # 7 6 Bit Name Notes Read/Write - - Reset 0 0 Bit [7:2]: Reserved Bit [1:0]: ...
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Figure 10. GPIO Port 1 Mode0 Register (Address 0x0C) Bit # 7 6 Bit Name Read/Write - - Reset 0 0 Bit [7:2]: Reserved Bit [1:0]: P1[1:0] Mode Port Pin Mode 0 is logic HIGH Figure 11. ...
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Table 3. Ports 0 and 1 Output Control Truth Table Data Register Mode1 Auxiliary Input Port Port 2 serves as an auxiliary input port as shown in Figure ...
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Send and update the data toggle bit (Data1/0). ■ Bit stuffing/unstuffing. ■ Firmware is required to handle the rest of the USB interface with the following tasks: Coordinate enumeration by decoding USB device requests. ■ Fill and empty the FIFOs. ...
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Firmware can clear the Bus Activity bit, but only the SIE can set it. The 1.024-ms timer interrupt service routine is normally used to check and ...
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USB Device The supports one USB Device Address with two endpoints: EP0 and EP1. Figure 14. USB Device Address Register (Address 0x10) Bit # 7 6 Bit Name Device Address Enable Read/Write R/W R/W Reset either USB ...
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Bit 6: IN Received valid IN packet has been received. This bit is updated to ‘1’ after the last received packet transaction. This bit is cleared by any non-locked writes to the register. 0 ...
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Bit 7: Data Toggle This bit selects the DATA packet's toggle state. For IN trans- actions, firmware must set this bit to the select the transmitted Data Toggle. For OUT or SETUP transactions, the hardware sets this bit to the ...
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Figure 18. Diagram of USB - PS/2 System Connections Port 2.0 VREG Enable Port 2.5 12-bit Free-running Timer The 12-bit timer operates with a 1-μs tick, provides two interrupts (128μs and 1.024ms) and allows the firmware to directly time events ...
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Bit [7:4]: Reserved Bit [3:0]: Timer upper 4 bits Processor Status and Control Register Figure 22. Processor Status and Control Register (Address 0xFF) Bit # 7 6 Bit ...
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No event detected since last cleared by firmware or LVR/WDR. Bit 4: LVR/BOR Reset The Low-voltage or Brown-out Reset is set to ‘1’ during a power-on reset. Firmware can check bits 4 and 6 in the reset handler ...
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Interrupt Vectors The Interrupt Vectors supported by the device are listed in Table 5. The highest priority interrupt is #1 (USB Bus Reset / PS/2 activity), and the lowest priority interrupt is #11 (Wake-up Timer). Although Reset is not an ...
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GPIO edge, while setting a Polarity bit to ‘1’ allows an interrupt on a rising GPIO edge. The Polarity Registers reset to 0 and are shown in Figure for Port 0 and Figure 29 for Port 1. All of the ...
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Figure 25. Interrupt Controller Logic Block Diagram CLR Enable [0] USB- (Reg 0x20) CLK PS/2 Int CLR Enable [1] (Reg 0x21) EP1 CLK Int CLR Enable [7] (Reg 0x20) Wake-up CLK ...
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Bit [7:0]: P1 [7:0] Interrupt Enable 1 = Enables GPIO interrupts from the corresponding input pin Disables GPIO interrupts from the corresponding input pin. Figure 28. Port 0 Interrupt Polarity Register (Address 0x06) Bit # 7 6 Bit ...
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USB Mode Tables The following tables give details on mode setting for the USB Serial Interface Engine (SIE) for both the control endpoint (EP0) and non-control endpoint (EP1). Table 6. USB Register Mode Encoding for Control and Non-Control Endpoint Mode ...
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An 'Ignore' means that the device sends no handshake tokens. An 'Accept' means that the SIE will respond with an ACK to a valid SETUP transaction. Comments Column: Some Mode Bits are automatically changed by the SIE in response to ...
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Table 8. Details of Modes for Differing Traffic Conditions End Point Mode Rcved Cou Token nt Buffer Dval SETUP Packet (if accepting) <= See6 SETUP 10 data valid See6 SETUP > 10 junk x See 6 ...
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Table 8. Details of Modes for Differing Traffic Conditions(continued) End Point Mode OUT > OUT x UC invalid Control Read ACK ...
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Table 8. Details of Modes for Differing Traffic Conditions(continued) End Point Mode < OUT 10 UC valid OUT > OUT x UC invalid 1 0 ...
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Register Summary Address Register Name Bit 7 0x00 Port 0 Data 0x01 Port 1 Data 0x02 Port 2 Data Reserved 0x0A GPIO Port 0 Mode 0 0x0B GPIO Port 0 Mode 1 0x0C GPIO Port 1 Mode 0 0x0D GPIO ...
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Absolute Maximum Ratings Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied...... –0°C to +70°C Supply voltage on V relative to V ............–0.5V to +7. Input Voltage .................................. –0. Voltage Applied to ...
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Parameter V Differential Input Sensitivity DI V Differential Input Common Mode Range CM V Single Ended Receiver Threshold SE C Transceiver Capacitance IN I Hi-Z State Data Line Leakage LO R External Bus Pull-up resistance (D– External Bus ...
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Switching Characteristics Parameter Description Internal Clock Mode F Internal Clock Frequency ICLK F Internal Clock Frequency, USB ICLK2 mode External Oscillator Mode T Input Clock Cycle Time CYC T Clock HIGH Time CH T Clock LOW Time CL Reset Timing ...
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CLOCK crs V ol D− T PERIOD Differential Data Lines Document #: 38-08028 Rev. *D Figure 31. Clock Timing T CYC Figure 32. USB Data Signal Timing ...
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Figure 34. Differential to EOP Transition Skew and EOP Width T PERIOD Crossover Differential Data Lines PERIOD Differential Data Lines Document #: 38-08028 Rev. *D Crossover Point Extended Point Diff. Data to SE0 Skew + T ...
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... Ordering Information EPROM Ordering Code Size CY7C63231A-SXC 3 KB CY7C63231A-PXC 3 KB CY7C63221A- Package Diagrams Document #: 38-08028 Rev. *D Package Name Package Type S1 18-Pin Small Outline Package Pb-free P3 18-Pin (300-Mil) PDIP Pb-free - 18-Pad DIE Form Figure 36. 16-Pin (300-Mil) Molded DIP P1 CY7C63221/31A Operating Range Commercial ...
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Document #: 38-08028 Rev. *D Figure 37. 18-Pin (300-Mil) Molded SOIC S1 Figure 38. 18-Pin (300-Mil) Molded DIP P3 CY7C63221/31A 51-85023 *C 51-85010-C Page [+] Feedback ...
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Die Step: 2031.0 x 2279.0 microns Pad Size microns Table 9 below shows the die pad coordinates for the CY7C63221A-XC. The center location of each bond pad is relative to the center of the die which has ...
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... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...