CY7C63231A-PXC Cypress Semiconductor Corp, CY7C63231A-PXC Datasheet - Page 38

• Manufacturer Part Number: CY7C63231A-PXC
• Description: IC MCU 3K USB LS PERIPH 18-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63231A-PXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (3 kB)
• Controller Series: CY7C632xx
• Ram Size: 96 x 8
• Interface: USB
• Number Of I /o: 10
• Voltage - Supply: 3.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Processor Series: CY7C63xx
• Core: M8B
• Data Bus Width: 16 bit
• Program Memory Size: 3 KB
• Data Ram Size: 96 B
• Interface Type: PS2, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 10
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Register Summary
Document #: 38-08028 Rev. *D
Address
0x0A
0x0B
0x0C
0x0D
0x11,
0x00
0x01
0x02
0x04
0x05
0x06
0x07
0xF8
0x10
0x12
0x14
0x13
0x1F
0x20
0x21
0x24
0x25
0xFF
Port 0 Data
Port 1 Data
Port 2 Data
GPIO Port 0 Mode 0
GPIO Port 0 Mode 1
GPIO Port 1 Mode 0
GPIO Port 1 Mode 1
Port 0 Interrupt Enable
Port 1 Interrupt Enable
Port 0 Interrupt Polarity
Port 1 Interrupt Polarity
Clock Configuration
USB Device Address
EP0 Mode
EP1 Mode Register
EP0 and 1Counter
USB Status and Control
Global Interrupt Enable
Endpoint Interrupt Enable
Timer LSB
Timer (MSB)
Process Status & Control
Register Name
Ext. Clock
Received
Wake-up
Resume
Data 0/1
Interrupt
Address
Pending
SETUP
Enable
Pull-up
Enable
Enable
Device
STALL
Toggle
Delay
Bit 7
PS/2
IRQ
Reserved
Watch Dog
Data Valid
Received
Interrupt
Enable
Enable
VREG
GPIO
Reset
Bit 6
IN
Wake-up Timer Adjust Bit [2:0]
Reserved
Reserved
Reset-PS/2
D+(SCLK)
Received
Interrupt
Interrupt
Activity
Mode
Event
State
Bit 5
OUT
USB
Bus
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
D- (SDATA)
Transaction
Transaction
P0[7:0] Interrupt Polarity
P0[7:0] Interrupt Enable
Reserved
Reserved
LVR/BOR
ACKed
ACKed
Reset
State
Bit 4
P0[7:0] Mode0
P0[7:0] Mode1
Timer Bit [7:0]
P0
Device Address
Low Voltage
Reserved
USB Bus
Suspend
Disable
Activity
Reset
Bit 3
P2.2(Int Clk
Mode only)
Precision
1.024 ms
Clocking
Interrupt
Interrupt
Enable
Enable
Enable
Sense
Bit 2
USB
Timer Bit [11:8]
Byte Count
Mode Bit
Mode Bit
D+/D- Forcing Bit
P2.1 (Int Clk
Mode only)
P1[1:0] Interrupt Polarity
P1[1:0] Interrupt Enable
Reserved
Interrupt
Interrupt
Internal
Disable
Enable
Enable
Output
128 μs
Clock
Bit 1
EP1
P1[1:0] Mode0
P1[1:0] Mode1
P1[1:0]
Reset-PS/2
Activity Intr.
P2.0 Vreg
Oscillator
Pin State
USB Bus
Interrupt
External
Enable
Enable
Enable
Bit 0
EP0
Run
CY7C63221/31A
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--
B
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Both(B)
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Page 38 of 47
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Default/
Section
Reset
See
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