CY7C63231A-PXC Cypress Semiconductor Corp, CY7C63231A-PXC Datasheet - Page 33

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CY7C63231A-PXC

Manufacturer Part Number
CY7C63231A-PXC
Description
IC MCU 3K USB LS PERIPH 18-DIP
Manufacturer
Cypress Semiconductor Corp
Series
enCoRe™r
Datasheets

Specifications of CY7C63231A-PXC

Applications
USB Microcontroller
Core Processor
M8B
Program Memory Type
OTP (3 kB)
Controller Series
CY7C632xx
Ram Size
96 x 8
Interface
USB
Number Of I /o
10
Voltage - Supply
3.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
18-DIP (0.300", 7.62mm)
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Processor Series
CY7C63xx
Core
M8B
Data Bus Width
16 bit
Program Memory Size
3 KB
Data Ram Size
96 B
Interface Type
PS2, USB
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
10
Number Of Timers
1
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C63231A-PXC
Manufacturer:
CYP
Quantity:
485
Part Number:
CY7C63231A-PXC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Bit 1: 128-µs Interrupt Enable
Bit 0: USB Bus Reset - PS/2 Interrupt Enable
Bit [7:3]: Reserved.
Bit [2:1]: EP1 Interrupt Enable
Refer to Table 20-1 for more information.
Bit 0: EP0 Interrupt Enable
Document #: 38-08028 Rev. *B
Read/Write
Bit Name
The 128-µs interrupt is another source of timer interrupt from the free-running timer. The user should disable both timer
interrupts (128-µs and 1.024-ms) before going into the suspend mode to avoid possible conflicts between servicing the timer
interrupts first or the suspend request first when waking up.
1 = Enable. Periodic interrupts will be generated approximately every 128 µs.
0 = Disable.
The function of this interrupt is selectable between detection of either a USB bus reset condition, or PS/2 activity. The selection
is made with the USB-PS/2 Interrupt Mode bit in the USB Status and Control Register (Figure 13-1). In either case, the interrupt
will occur if the selected condition exists for 256 µs, and may occur as early as 128 µs.
A USB bus reset is indicated by a single-ended zero (SE0) on the USB D+ and D– pins. The USB Bus Reset interrupt occurs
when the SE0 condition ends. PS/2 activity is indicated by a continuous LOW on the SDATA pin. The PS/2 interrupt occurs
as soon as the long LOW state is detected.
During the entire interval of a USB Bus Reset or PS/2 interrupt event, the USB Device Address register is cleared.
The Bus Reset/PS/2 interrupt may occur 128µs after the bus condition is removed.
1 = Enable
0 = Disable
The non-control endpoint interrupt (EP1) is generated when:
1 = Enable
0 = Disable
If enabled, the control endpoint interrupt is generated when:
1 = Enable EP0 interrupt
0 = Disable EP0 interrupt
Reset
• The USB host writes valid data to an endpoint FIFO. However, if the endpoint is in ACK OUT modes, an interrupt is generated
• The device SIE sends a NAK or STALL handshake packet to the USB host during the host attempts to read data from the
• The device receives an ACK handshake after a successful read transaction (IN) from the host.
• The device SIE sends a NAK or STALL handshake packet to the USB host during the host attempts to write data (OUTs)
• The endpoint 0 mode is set to accept a SETUP token.
• After the SIE sends a 0 byte packet in the status stage of a control transfer.
• The USB host writes valid data to an endpoint FIFO. However, if the endpoint is in ACK OUT modes, an interrupt is generated
• The device SIE sends a NAK or STALL handshake packet to the USB host during the host attempts to read data from the
• The device SIE sends a NAK or STALL handshake packet to the USB host during the host attempts to write data (OUTs)
Bit #
regardless of data packet validity (i.e., good CRC). Firmware must check for data validity.
endpoint (INs).
to the endpoint FIFO.
regardless of what data is received. Firmware must check for data validity.
endpoint (INs).
to the endpoint FIFO.
7
0
-
Figure 19-2. Endpoint Interrupt Enable Register (Address 0x21)
6
0
-
FOR
FOR
5
0
-
Reserved
4
0
-
3
0
-
2
0
-
CY7C63221/31A
enCoRe™ USB
Interrupt
Enable
EP1
R/W
1
0
Page 33 of 50
Interrupt
Enable
EP0
R/W
0
0
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