CY7C68014A-100AXC Cypress Semiconductor Corp, CY7C68014A-100AXC Datasheet - Page 44

• Manufacturer Part Number: CY7C68014A-100AXC
• Description: IC MCU USB PERIPH HI SPD 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68014A-100AXC

• Program Memory Type: ROMless
• Package / Case: 100-LQFP
• Applications: USB Microcontroller
• Core Processor: 8051
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 40
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Processor Series: CY7C68xx
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/USART/USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3684
• Minimum Operating Temperature: 0 C
• Controller Family/series: (8051) USB
• Core Size: 8 Bit
• No. Of I/o's: 40
• Program Memory Size: 16KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, USART, USB
• Rohs Compliant: Yes
• Package: 100TQFP
• Device Core: 8051
• Family Name: FX2LP
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1670

9.1 Slave FIFO Synchronous Read
Table 9-1. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK
Table 9-2. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK
Document #: 38-08032 Rev. *T
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IFCLK
SRD
RDH
OEon
OEoff
XFLG
XFD
IFCLK
SRD
RDH
OEon
OEoff
XFLG
XFD
Parameter
Parameter
IFCLK period
SLRD to clock setup time
Clock to SLRD hold time
SLOE turn on to FIFO data valid
SLOE turn off to FIFO data hold
Clock to FLAGS output propagation delay
Clock to FIFO data output propagation delay
IFCLK period
SLRD to clock setup time
Clock to SLRD hold time
SLOE turn on to FIFO data valid
SLOE turn off to FIFO data hold
Clock to FLAGS output propagation delay
Clock to FIFO data output propagation delay
FLAGS
SLOE
SLRD
DATA
IFCLK
Figure 9-7. Slave FIFO Synchronous Read Timing Diagram
Description
Description
t
OEon
N
t
SRD
t
IFCLK
t
RDH
t
XFLG
t
XFD
N+1
20.83
20.83
18.7
12.7
Min
Min
3.7
0
–
–
–
–
–
–
–
–
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
t
OEoff
[21]
[21]
[20]
Max
10.5
10.5
Max
10.5
10.5
13.5
200
9.5
15
11
–
–
–
–
–
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 44 of 67
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