CY7C68014A-100AXC Cypress Semiconductor Corp, CY7C68014A-100AXC Datasheet - Page 49

• Manufacturer Part Number: CY7C68014A-100AXC
• Description: IC MCU USB PERIPH HI SPD 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68014A-100AXC

• Program Memory Type: ROMless
• Package / Case: 100-LQFP
• Applications: USB Microcontroller
• Core Processor: 8051
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 40
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Processor Series: CY7C68xx
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/USART/USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3684
• Minimum Operating Temperature: 0 C
• Controller Family/series: (8051) USB
• Core Size: 8 Bit
• No. Of I/o's: 40
• Program Memory Size: 16KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, USART, USB
• Rohs Compliant: Yes
• Package: 100TQFP
• Device Core: 8051
• Family Name: FX2LP
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1670

9.13 Slave FIFO Output Enable
Table 9-1. Slave FIFO Output Enable Parameters
9.14 Slave FIFO Address to Flags/Data
Table 9-1. Slave FIFO Address to Flags/Data Parameters
9.15 Slave FIFO Synchronous Address
Table 9-1. Slave FIFO Synchronous Address Parameters
Document #: 38-08032 Rev. *T
t
t
t
t
t
t
t
OEon
OEoff
XFLG
XFD
IFCLK
SFA
FAH
Parameter
Parameter
Parameter
SLOE assert to FIFO DATA output
SLOE deassert to FIFO DATA hold
FIFOADR[1:0] to FLAGS output propagation delay
FIFOADR[1:0] to FIFODATA output propagation delay
Interface clock period
FIFOADR[1:0] to clock setup time
Clock to FIFOADR[1:0] hold time
SLCS/FIFOADR [1:0]
Figure 9-16. Slave FIFO Synchronous Address Timing Diagram
Figure 9-15. Slave FIFO Address to Flags/Data Timing Diagram
FIFOADR [1.0]
Figure 9-14. Slave FIFO Output Enable Timing Diagram
DATA
SLOE
FLAGS
DATA
IFCLK
Description
Description
Description
[21]
t
OEon
t
XFLG
t
XFD
N
t
SFA
N+1
t
FAH
t
OEoff
20.83
Min
Min
Min
25
10
–
–
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
[20]
[20]
Max
10.5
10.5
Max
10.7
14.3
[20]
Max
200
–
–
Unit
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
Page 49 of 67
[+] Feedback