ADE7166ASTZF8 Analog Devices Inc, ADE7166ASTZF8 Datasheet - Page 139

• Manufacturer Part Number: ADE7166ASTZF8
• Description: IC ENERGY METER 1PHASE 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7166ASTZF8

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (8 kB)
• Controller Series: ADE71xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 support a fully licensed I
interface is implemented as a full hardware master.
SDATA (P0.4/MOSI/SDATA) is the data I/O pin, and SCLK
(P0.6/SCLK/T0) is the serial clock. These two pins are shared
with the MOSI and SCLK pins of the on-chip SPI interface.
Therefore, the user can enable only one interface or the other
on these pins at any given time. The SCPS bit (Bit 5) in the
configuration SFR (CFG, Address 0xAF) selects which
peripheral is active.
The two pins used for data transfer, SDATA and SCLK, are
configured in a wire-AND format that allows arbitration in
a multimaster system.
The transfer sequence of an I
initiating a transfer by generating a start condition while the bus
is idle. The master transmits the address of the slave device and
the direction of the data transfer in the initial address transfer. If
the slave acknowledges, the data transfer is initiated. This continues
until the master issues a stop condition and the bus becomes idle.
SERIAL CLOCK GENERATION
The I
transfer. The master channel can be configured to operate in
fast mode (256 kHz) or standard mode (32 kHz).
Table 151. I
SFR Address
0x9A
0x9B
0xE8
0xE9
0xEA
Table 152. I
Bit
7
[6:5]
[4:0]
Table 153. I
Bit
[7:1]
0
2
C-COMPATIBLE INTERFACE
2
C master in the system generates the serial clock for a
Bit Address
0xEF
0xEE to 0xED
0xEC to 0xE8
Mnemonic
I2CSLVADR
I2CR_W
2
2
2
C SFR List
C Mode SFR (I2CMOD, Address 0xE8)
C Slave Address SFR (I2CADR, Address 0xE9)
Mnemonic
SPI2CTx
SPI2CRx
I2CMOD
I2CADR
SPI2CSTAT
Default
0
0
Mnemonic
I2CEN
I2CR
I2CRCT
2
C system consists of a master device
2
C interface. The I
Description
Address of the I
Command bit for read or write. When this bit is set to Logic 1, a read command is transmitted on the
I
When this bit is set to Logic 0, a write command is transmitted on the I
in the SPI2CTx SFR.
2
C bus. Data from the slave in the SPI2CRx SFR (Address 0x9B) is expected after a command byte.
0
0
0
Default
R/W
W
R
R/W
R/W
R/W
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Description
I
I2CADR SFR starts a communication.
I
I2CR
00
01
10
11
Configures the length of the I
I2CRCT bits + 1 byte have been read, or if an error occurs.
2
2
C enable bit. When this bit is set to Logic 1, the I
C SCLK frequency.
2
C slave being addressed. Writing to this register starts the I
2
C
Length
8
8
8
8
8
Rev. B | Page 139 of 152
Result
f
f
f
f
CORE
CORE
CORE
CORE
/16 = 256 kHz if f
/32 = 128 kHz if f
/64 = 64 kHz if f
/128 = 32 kHz if f
Default
0
0
0
0
The bit rate is defined in the I2CMOD SFR as follows:
SLAVE ADDRESSES
The I
the slave device ID. The LSB of this register contains a
read/write request. A write to this SFR starts the I
communication.
I
The I
•
•
•
•
•
Because the SPI and I
they also share the same SFRs, such as the SPI2CTx and SPI2CRx
SFRs. In addition, the I2CMOD, I2CADR, and SPI2CSTAT, and
SPI2CTx SFRs are shared with the SPIMOD1, SPIMOD2, and
SPISTAT SFRs, respectively.
2
C REGISTERS
I2CMOD
SPI2CSTAT
I2CADR
SPI2CTx
SPI2CRx
2
2
2
f
C received FIFO buffer. The I
C slave address SFR (I2CADR, Address 0xE9) contains
C peripheral interface consists of five SFRs:
SCLK
CORE
CORE
CORE
CORE
=
= 4.096 MHz.
= 4.096 MHz.
= 4.096 MHz.
= 4.096 MHz.
16
Description
SPI/I
SPI/I
I
I
I
2
2
2
×
C mode (see Table 152).
C slave address (see Table 153).
C interrupt status register (see Table 154).
f
2
CORE
I
2
2
2
C transmit buffer (see Table 146).
C receive buffer (see Table 147).
CR
2
: 1 [
C serial interfaces share the same pins,
] 0
2
C interface is enabled. A write to the
2
C bus. Data to slave is expected
2
C peripheral stops when the
2
C transmission (read or write).
2
C