Z9025106PSC Zilog, Z9025106PSC Datasheet - Page 21

• Manufacturer Part Number: Z9025106PSC
• Description: IC 32K 8BIT DTC OTP 42-DIP
• Manufacturer: Zilog

Specifications of Z9025106PSC

• Applications: TV Controller
• Core Processor: Z8
• Program Memory Type: OTP (32 kB)
• Controller Series: Digital Television Controller (DTC)
• Ram Size: 300 x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 27
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 42-DIP (0.600", 15.24mm)
• Processor Series: Z902x
• Core: Z8
• Data Bus Width: 8 bit
• Program Memory Size: 32 KB
• Data Ram Size: 300 B
• Interface Type: I2C
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 27
• Mounting Style: Through Hole
• On-chip Adc: 4 bit, 4 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 4
Address Description
Address Description
BANK 4
Address Description
00h-0Fh Gen. Pur. Reg.
BANK A
BANK C
0Ah
0Bh
0Ch
0Dh
0Eh
0Ah
0Bh
0Ch
0Dh
0Eh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Fh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Fh
OSD Control Register(OSD_CNTL)
Vertical Position Register(VERT_POS)
Horizontal Position Register(HOR_POS)
Display Attribute Register(DISP_ATTR)
Row Space Register (ROW_SPACE)
Fade Position1 Register(FADE_POS1)
Fade Position2 Regisiter(FADE_POS2)
Second Color Control
Register(SNDCLR_CNTRL)
Second Color Position
Register(SNDCLR_POS)
Color Palette0 Register(CLR_P0)
Color Palette1 Register(CLR_P1)
Color Palette2 Register(CLR_P2)
Color Palette3 Register(CLR_P3)
Color Palette4 Register(CLR_P4)
Color Palette5 Register(CLR_P5)
Color Palette6 Register(CLR_P6)
3-bit ADC Data Register(3ADC_DTA)
Timer Control Register0(TCR0)
Timer Control Register1(TCR1)
IR Capture Register0(IR_CP0)
IR Capture Register1(IR_CP1)
Port4 Data Register(PRT4_DTA)
Port4 Direction Register(PRT4_DRT)
Interrupt Status Register(INT_ST)
Port4 Pin_out Selection Register(PIN_SLT)
Color Index Register(CLR_IDX)
I2C Data Register(I
I2C Command Register(I
I2C Control Register(I
Register File Map
2
BANK 5
00h-0Fh Gen. Pur. Reg. 00h-0Fh
Address Description
C_DATA)
2
C_CNTL)
2
C_CMD)
32 KB Television Controller with OSD
Address Description
Address Description
BANK 6
BANK B
BANK F
Address
0Ah
0Bh
0Ch
0Dh
0Eh
0Ah
0Bh
0Ch
0Dh
0Eh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Fh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Fh
PWM11-High Data Register(PWM11H)
PWM11-Low Data Register(PWM11L)
PWM1 Data Register(PWM1)
PWM2 Data Register(PWM2)
PWM3 Data Register(PWM3)
PWM4 Data Register(PWM4)
PWM5 Data Register(PWM5)
PWM6(6-bit) Data Register(PWM6_6)
PWM7 Data Register(PWM7)
PWM8 Data Register(PWM8)
PWM9 Data Register(PWM9)
PWM10 Data Register(PWM10)
Port 5 Data Register(PRT5_DTA)
PWM Mode Register(P_MODE)
Port 5 Direction Register(PRT5_DRT)
Port Configuration Register(PCON)
4-bit ADC Data Register (4ADC_DTA)
Port6 Direction Register(PRT6_DRT)
Port6 Data Register (PRT6_DTA)
Mesh Column Start Register(MC_ST)
Mesh Column End Register(MC_END)
Mesh Row Enable Register(MR_EN)
Mesh Control Register(MC_REG)
PWM6 High Data Register(PWM6H_14)
PWM6 Low Data Register (PWM6L_14)
Stop Mode Register(SMR)
WDT Mode Register(WDTMR)
Gen. Pur. Reg. 00h-0Fh Gen. Pur. Reg.
Description
BANK 7
Address Description
PS001301-0800
13