Z9025106PSC Zilog, Z9025106PSC Datasheet - Page 7
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Z9025106PSC
Manufacturer Part Number
Z9025106PSC
Description
IC 32K 8BIT DTC OTP 42-DIP
Manufacturer
Zilog
Datasheet
1.Z9025106PSC.pdf
(97 pages)
Specifications of Z9025106PSC
Applications
TV Controller
Core Processor
Z8
Program Memory Type
OTP (32 kB)
Controller Series
Digital Television Controller (DTC)
Ram Size
300 x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
27
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
42-DIP (0.600", 15.24mm)
Processor Series
Z902x
Core
Z8
Data Bus Width
8 bit
Program Memory Size
32 KB
Data Ram Size
300 B
Interface Type
I2C
Maximum Clock Frequency
6 MHz
Number Of Programmable I/os
27
Mounting Style
Through Hole
On-chip Adc
4 bit, 4 Channel
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
List of Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Z90255 Production Device Pin Assignment ............................................... 6
Single-Purpose Pin Descriptions ................................................................ 7
Multiplexed Pin Descriptions....................................................................... 8
Register File Map...................................................................................... 13
Watch-Dog Timer Mode Register 0Fh: Bank F ......................................... 15
Stop Mode Recovery (SMR) Register 0Bh: Bank F (SMR) ...................... 19
Stop Mode Recovery Source .................................................................... 20
OSD Control Register 00h:Bank A (OSD_CNTL)..................................... 22
Vertical Position Register 01h:Bank A (VERT_POS) ............................... 24
Horizontal Position Register 02h:Bank A (HOR_POS) ............................. 25
Second Color Control Register 07h:Bank A (SNDCLR_CNTRL) ............. 26
Second Color Register 08h:Bank A (SNDCLR)........................................ 26
Mesh Column Start Register 04h: Bank F (MC_St) .................................. 29
Mesh Column End Register 05h: Bank F (MC_End) ................................ 30
Mesh Row Enable Register 06h: Bank F (MR_En) .................................. 30
Mesh Control Register 07h: Bank F (MC_Reg) ........................................ 31
BGR Mesh Colors ..................................................................................... 33
Fade Position Register 1 05h: Bank A (FADE_POS1) ............................. 35
Fade Position Register 2 06h: Bank A (FADE_POS2) ............................. 35
Row Space Register 04h: BankA (ROW_SPACE) ................................... 36
RGB Colors ............................................................................................... 40
Display Attribute Register 03h: Bank A (DISP_ATTR) ............................. 41
VRAM Structure and Memory Map ........................................................... 43
Color Palette Selection Bits ...................................................................... 45
Color Index Register 09h: Bank C (CLR_IDX).......................................... 45
Color Palette 0 Register 09h: Bank A (CLR_P0) ...................................... 46
Color Palette 1 Register 0Ah: Bank A (CLR_P1) ...................................... 46
Color Palette 2 Register 0Bh: Bank A (CLR_P2) ...................................... 47
Color Palette 3 Register 0Ch: Bank A (CLR_P3) ..................................... 47
Color Palette 4 Register 0Dh: Bank A (CLR_P4) ..................................... 47
Color Palette 5 Register 0Eh: Bank A (CLR_P5) ...................................... 48
Color Palette 6 Register 0Fh: Bank A (CLR_P6) ...................................... 48
Row Attribute Register (ROW_ATTR) ...................................................... 49
HV Interrupt Status Register 07h: Bank C (INT_ST) ................................ 50
Master I2C Control Register 0Ch: Bank C (I2C_CNTL) ........................... 54
Master I2C Command Register 0Bh: Bank C (I2C_CMD) ........................ 55
32 KB Television Controller with OSD
PS001301-0800
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