Z9025106PSC Zilog, Z9025106PSC Datasheet - Page 63
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Z9025106PSC
Manufacturer Part Number
Z9025106PSC
Description
IC 32K 8BIT DTC OTP 42-DIP
Manufacturer
Zilog
Datasheet
1.Z9025106PSC.pdf
(97 pages)
Specifications of Z9025106PSC
Applications
TV Controller
Core Processor
Z8
Program Memory Type
OTP (32 kB)
Controller Series
Digital Television Controller (DTC)
Ram Size
300 x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
27
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
42-DIP (0.600", 15.24mm)
Processor Series
Z902x
Core
Z8
Data Bus Width
8 bit
Program Memory Size
32 KB
Data Ram Size
300 B
Interface Type
I2C
Maximum Clock Frequency
6 MHz
Number Of Programmable I/os
27
Mounting Style
Through Hole
On-chip Adc
4 bit, 4 Channel
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Table 36 Master I
Software puts data to be transmitted into I
received data from it. Bit 7 in this register is used as an acknowledge bit when
receiving data from a Slave. Bit 0 of I
acknowledgment bit generated by the Slave. Refer to Table 38.
Table 37 Master I
Bit
R/W
Reset
Note: R = Read W = Write X = Indeterminate
Bit/
Field
Reserved
I
Reserved
Reset
Busy
Bit
R/W
Reset
Note: R = Read W = Write X = Indeterminate
Bit/
Field
Data
2
C Command
Bit
Position
7,6,5,4,3,2,1,0
7
7
2
Bit
Position
7
6, 5, 4
3, 2
1
0
2
R/W
R/W
C Command Register 0Bh: Bank C (I
C Data Register 0Ah: Bank C (I
x
0
6
6
R/W
R/W
0
x
R/W Value
R
W
R/W
W
W
W
W
W
R
R
R
R
R
5
5
R/W
R/W
x
0
Value Description
2
0
1
0
1
C_DATA register contains an
4
4
32 KB Television Controller with OSD
R/W
R/W
2
0
x
C Data Register (Table 37) and reads
Description
Received data
Data to be sent
Return 1
No Effect
Return 1
See Table 35
Return 1
No Effect
Return 1
No Effect
Reset I
Idle
Busy
No Effect
3
3
2
C_DATA)
2
R/W
R/W
C interface
0
x
2
C_CMD)
2
2
R/W
R/W
0
x
1
1
R/W
R/W
PS001301-0800
0
x
0
0
R/W
R/W
0
0
55
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