Z9025106PSC Zilog, Z9025106PSC Datasheet - Page 59
![no-image](/images/manufacturer_photos/0/7/729/zilog_sml.jpg)
Z9025106PSC
Manufacturer Part Number
Z9025106PSC
Description
IC 32K 8BIT DTC OTP 42-DIP
Manufacturer
Zilog
Datasheet
1.Z9025106PSC.pdf
(97 pages)
Specifications of Z9025106PSC
Applications
TV Controller
Core Processor
Z8
Program Memory Type
OTP (32 kB)
Controller Series
Digital Television Controller (DTC)
Ram Size
300 x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
27
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
42-DIP (0.600", 15.24mm)
Processor Series
Z902x
Core
Z8
Data Bus Width
8 bit
Program Memory Size
32 KB
Data Ram Size
300 B
Interface Type
I2C
Maximum Clock Frequency
6 MHz
Number Of Programmable I/os
27
Mounting Style
Through Hole
On-chip Adc
4 bit, 4 Channel
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
51
are ignored. When the Palette Mode value is 1, the Color Palette Selection Bits
are used, unless they are set to 0s. In that case, the values in the ROW_ATTR
register are used.
Bit 2, Horizontal Interrupt Enable, disables or enables the horizontal (H
)
SYNC
interrupt.
Bit 1, Vertical Interrupt, has different meanings depending on its Read and Write
status. In Read State, a value of 0 indicates that a vertical interrupt was not
issued; a value of 1 indicates that a vertical interrupt was issued. In Write State, a
value of 0 has no effect; a value of
resets the vertical interrupt flag.
1
Bit 0, Horizontal Interrupt, has different meanings depending on its status. In
Read State, a value of 0 indicates that a horizontal interrupt was not issued; a
value of 1 indicates that a horizontal interrupt was issued. In Write State, a value
of
has no effect; a value of
resets the horizontal interrupt flag.
0
1
When an interrupt is issued while another interrupt is processing, the last-issued
interrupt is pended. The interrupt-flag bit which is in service (the interrupt issued
first) must be cleared or serviced before the pended interrupt can be processed
(see SNDCLR(6)).
PS001301-0800