PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 655
PNX1500E/G,557
Manufacturer Part Number
PNX1500E/G,557
Description
IC MEDIA PROC 240MHZ 456-BGA
Manufacturer
NXP Semiconductors
Specifications of PNX1500E/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.14 V ~ 1.26 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Ram Size
-
Lead Free Status / Rohs Status
Compliant
Other names
568-1296
935277746557
PNX1500E/G
935277746557
PNX1500E/G
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PNX15XX_SER_3
Product data sheet
3.2.7 VLD DMA Run-Level Current Write Address (VLD_RL_ADR)
3.2.8 VLD DMA Run-Level Current Write Count
3.2.9 VLD Command (VLD_COMMAND)
The CPU writes the main memory run-level pair buffer address in the VLD_RL_ADR
register in order to output the run-level pairs in main memory. The VLD updates this
address whenever data is transferred to main memory via the DMA logic. The
address always represents the next write address of the macroblock header data.
The buffer address must be 32-bit aligned.
The CPU writes the main memory run-level pairs buffer size formatted as the number
of words into the VLD_RL_CNT register in order to output the run-level pairs data in
main memory. The VLD updates the buffer size whenever data is transferred to main
memory via the DMA logic. The buffer size always represents the remaining empty
buffer space.
This read/write register indicates the next action to be taken by the VLD. A command
is sent to the VLD by writing the corresponding 4-bit command code in the
COMMAND field of the VLD_COMMAND register. Some commands require an
associated count value which resides in the least significant 8 bits of this register. The
following nine VLD commands are currently available:
•
•
•
•
•
•
•
•
•
Shift the video bitstream by “count” bits (where “count” is given in the COUNT
field of the register and must be between 0 and 15 inclusive).
Parse “count” macroblocks (where “count” is given in the COUNT field of the
register and must be between 0 and 255 inclusive).
Search for the next start code.
Reset the Variable Length Decoder.
Initialize the VLD (to clear the VLD_BIT_CNT register).
Search for the specific 8-bit start code pattern given in the COUNT field of the
register.
Flush the VLD output buffers to main memory.
Parse one row of macroblocks.
Parse macroblocks continuously. (COUNT field is unused, but cannot be
programmed to 0.)
Rev. 3 — 17 March 2006
Chapter 21: MPEG-1 and MPEG-2 Variable Length Decoder
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
21-7
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