CY7C64613-80NC Cypress Semiconductor Corp, CY7C64613-80NC Datasheet - Page 14

• Manufacturer Part Number: CY7C64613-80NC
• Description: IC MCU USB EZ FX 8K RAM 80-PQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX™r

Specifications of CY7C64613-80NC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C646xx
• Ram Size: 8K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1312

3.2
Document #: 38-08005 Rev. **
Port B
128
30
31
32
79
80
81
CY7C646xx Pin Descriptions
80
16
17
18
47
48
49
52
29
30
31
11
PB0 or
PB1 or
PB2 or
PA5 or
FRD# or
RDY5 or
SLRD
PA6 or
RXD0OUT
PA7 or
RXD1OUT
T2 or
D[0] or
GDA[0] or
AFI [0]
T2EX or
D[1] or
GDA[1] or
AFI [1]
RXD1 or
D[2] or
GDA[2] or
AFI [2]
Name
Type
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
(continued)
Default
(PB0)
(PB1)
(PB2)
(PA5)
(PA6)
(PA7)
I
I
I
I
I
I
Multiplexed pin whose function is selected by the following bits:
PORTACFG.5, PORTACF2.5, and IFCONFIG[1..0].
PA5 is a bidirectional I/O port pin.
FRD# is the write strobe output for an external FIFO connected to
the data bus D[7..0]. If the FRD# pin is used, it should be externally
pulled up to V
on.
RDY5 is a GPIF input signal.
SLRD is the read strobe input for the slave FIFOs connected to
AFI[7..0] and/or BFI[7..0].
Multiplexed pin whose function is selected by the PORTACFG.6 bit.
PA6 is a bidirectional I/O port pin.
RXD0OUT is an active-HIGH signal from 8051 UART0. If
RXD0OUT is selected and UART0 is in mode 0, this pin provides
the output data for UART0 only when it is in sync mode. Otherwise
it is a 1.
Multiplexed pin whose function is selected by the PORTACFG.7 bit.
PA7 is a bidirectional I/O port pin.
RXD1OUT is an active-HIGH output from 8051 UART1. When
RXD1OUT is selected and UART1 is in mode 0, this pin provides
the output data for UART1 only when it is in sync mode. In modes
1, 2, and 3, this pin is HIGH.
The following descriptions apply to the PORT B pins:
D[7..0] is the 8051 data bus. This bus is optionally available on
PORT B pins to provide access to the 8051 data bus in smaller EZ-
USB II packages that do not bring out the 8051 address and data
buses.
GDA[7..0] is the GPIF A data bus.
AFI[7..0] is the bidirectional A-FIFO data bus.
Multiplexed pin whose function is selected by the following bits:
PORTBCFG.0 and IFCONFIG[1..0].
PB0 is a bidirectional I/O port pin.
T2 is the active-HIGH T2 input signal to 8051 Timer2, which pro-
vides the input to Timer2 when C/T2=1. When C/T2=0, Timer2 does
not use this pin.
AFI [0] is the bidirectional A-FIFO data bus.
Multiplexed pin whose function is selected by the following bits:
PORTBCFG.1 and IFCONFIG[1..0].
PB1 is a bidirectional I/O port pin.
T2EX is an active-HIGH input signal to the 8051 Timer2. T2EX re-
loads timer 2 on its falling edge. T2EX is active only if the EXEN2
bit is set in T2CON.
AFI [1] is the bidirectional A-FIFO data bus.
Multiplexed pin whose function is selected by the following bits:
PORTBCFG.2 and IFCONFIG[1..0].
PB2 is a bidirectional I/O port pin.
RXD1is an active-HIGH input signal for 8051 UART1, which pro-
vides data to the UART in all modes.
AFI [2] is the bidirectional A-FIFO data bus.
CC
to ensure that the read strobe is inactive at power-
Description
CY7C64601/603/613
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