CY7C63743-SC Cypress Semiconductor Corp, CY7C63743-SC Datasheet - Page 15

• Manufacturer Part Number: CY7C63743-SC
• Description: IC MCU 8K LS USB/PS-2 24-SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63743-SC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C637xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 16
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1325

Bit [7:0]: P0[7:0]
Bit [7:0]: P1[7:0]
Bit [7:0]: P0[7:0] Mode 0
Bit [7:0]: P0[7:0] Mode 1
Document #: 38-08022 Rev. *B
Figure 12-4. GPIO Port 0 Mode0 Register (Address 0x0A)
Figure 12-5. GPIO Port 0 Mode1 Register (Address 0x0B)
Figure 12-6. GPIO Port 1 Mode0 Register (Address 0x0C)
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Read/Write
Read/Write
Read/Write
Bit Name
Bit Name
Bit Name
Bit Name
Bit Name
1 = Port Pin is logic HIGH
0 = Port Pin is logic LOW
1 = Port Pin is logic HIGH
0 = Port Pin is logic LOW
1 = Port 0 Mode 0 is logic HIGH
0 = Port 0 Mode 0 is logic LOW
1 = Port Pin Mode 1 is logic HIGH
0 = Port Pin Mode 1 is logic LOW
Notes
Reset
Reset
Reset
Reset
Reset
Bit #
Bit #
Bit #
Bit #
Bit #
Figure 12-2. Port 0 Data (Address 0x00)
Figure 12-3. Port 1 Data (Address 0x01)
W
W
W
7
0
7
0
7
0
7
0
7
0
Pins 7:2 only in CY7C63743
W
W
W
6
0
6
0
6
0
6
0
6
0
W
W
W
5
0
5
0
5
0
5
0
5
0
P0[7:0] Mode0
P1[7:0] Mode0
P0[7:0] Mode1
W
W
W
4
0
4
0
4
0
4
0
4
0
P0
P1
FOR
FOR
W
W
W
3
0
3
0
3
0
3
0
3
0
W
W
W
2
0
2
0
2
0
2
0
2
0
Pins 1:0 in
W
W
W
all parts
1
0
1
0
1
0
1
0
1
0
W
W
W
0
0
0
0
0
0
0
0
0
0
Bit [7:0]: P1[7:0] Mode 0
Bit [7:0]: P1[7:0] Mode 1
Each pin can be independently configured as high-impedance
inputs, inputs with internal pull-ups, open drain outputs, or
traditional CMOS outputs with selectable drive strengths.
The driving state of each GPIO pin is determined by the value
written to the pin’s Data Register and by its associated Mode0
and Mode1 bits. Table 12-1 lists the configuration states
based on these bits. The GPIO ports default on reset to all
Data and Mode Registers cleared, so the pins are all in a
high-impedance state. The available GPIO output drive
strength are:
Note that open drain mode can be achieved by fixing the Data
and Mode1 Registers LOW, and switching the Mode0 register.
Input thresholds are CMOS, or TTL as shown in the table (See
Section 25.0 for the input threshold voltage in TTL or CMOS
modes). Both input modes include hysteresis to minimize
noise sensitivity. In suspend mode, if a pin is used for a
wake-up interrupt using an external R-C circuit, CMOS mode
is preferred for lowest power.
Figure 12-7. GPIO Port 1 Mode1 Register (Address 0x0D)
Read/Write
• Hi-Z Mode (Mode1 = 0 and Mode0 = 0)
• Low Sink Mode (Mode1 = 1, Mode0 = 0, and the pin’s Data
• Medium Sink Mode (Mode1 = 0, Mode0 = 1, and the pin’s
• High Sink Mode (Mode1 = 1, Mode0 = 1, and the pin’s Data
• High Drive Mode (Mode1 = 0 or 1, Mode0 = 1, and the pin’s
• Resistive Mode (Mode1 = 1, Mode0 = 0, and the pin’s Data
Bit Name
1 = Port Pin Mode 0 is logic HIGH
0 = Port Pin Mode 0 is logic LOW
1 = Port Pin Mode 1 is logic HIGH
0 = Port Pin Mode 1 is logic LOW
Q1, Q2, and Q3 (Figure 12-1) are OFF. The GPIO pin is not
driven internally. Performing a read from the Port Data Reg-
ister return the actual logic value on the port pins.
Register = 0)
Q1 and Q3 are OFF. Q2 is ON. The GPIO pin is capable of
sinking 2 mA of current.
Data Register = 0)
Q1 and Q3 are OFF. Q2 is ON. The GPIO pin is capable of
sinking 8 mA of current.
Register = 0)
Q1 and Q3 are OFF. Q2 is ON. The GPIO pin is capable of
sinking 50 mA of current.
Data Register = 1)
Q1 and Q2 are OFF. Q3 is ON. The GPIO pin is capable of
sourcing 2 mA of current.
Register = 1)
Q2 and Q3 are OFF. Q1 is ON. The GPIO pin is pulled up
with an internal 14-kΩ resistor.
Reset
Bit #
W
7
0
W
6
0
W
5
0
P1[7:0] Mode1
W
4
0
W
3
0
CY7C63722
CY7C63723
CY7C63743
W
2
0
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W
1
0
W
0
0