CY7C63743-SC Cypress Semiconductor Corp, CY7C63743-SC Datasheet - Page 3

• Manufacturer Part Number: CY7C63743-SC
• Description: IC MCU 8K LS USB/PS-2 24-SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63743-SC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C637xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 16
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1325

event, and subtracting the two values. The four capture timers
save a programmable 8 bit range of the free-running timer
when a GPIO edge occurs on the two capture pins (P0.0,
P0.1).
The CY7C637xx includes an integrated USB serial interface
engine (SIE) that supports the integrated peripherals. The
hardware supports one USB device address with three
endpoints. The SIE allows the USB host to communicate with
the function integrated into the microcontroller. A 3.3V
regulated output pin provides a pull-up source for the external
USB resistor on the D– pin.
4.0
5.0
Document #: 38-08022 Rev. *B
D–/SDATA,
D+/SCLK
P0[7:0]
P1[7:0]
XTALIN/P2.1
XTALOUT
V
V
VREG/P2.0
V
PP
CC
SS
Name
XTALIN/P2.1
VREG/P2.0
Pin Configurations
Pin Definitions
18-pin SOIC/PDIP
P0.0
P0.1
P0.2
P0.3
P1.0
VSS
VPP
CY7C63723
OUT
1
2
3
4
5
6
7
8
9
I/O
I/O
I/O
I/O
IN
18
17
16
15
14
13
12
11
10
15, 16, 17, 18
CY7C63723
1, 2, 3, 4,
P0.5
P0.4
P0.6
P0.7
P1.1
D+/SCLK
D–/SDATA
VCC
XTALOUT
18-Pin
5, 14
12
13
10
11
9
7
8
6
FOR
FOR
21, 22, 23, 24
17, 18, 19, 20
CY7C63743
1, 2, 3, 4,
5, 6, 7, 8,
24-Pin
15
16
12
13
10
14
XTALIN/P2.1
11
9
VREG/P2.0
24-pin SOIC/PDIP/QSOP
P0.0
P0.1
P0.2
P0.3
P1.0
P1.2
P1.4
P1.6
VSS
VPP
CY7C63743
22, 23, 24, 25
18, 19, 20, 21
CY7C63722
1
2
3
4
5
6
7
8
9
10
11
12
1, 2, 3, 4,
5, 6, 7, 8,
Top View
25-Pad
9, 10
16
17
13
14
15
12
11
24
23
22
21
20
19
18
17
16
15
14
13
The USB D+ and D– USB pins can alternately be used as PS/2
SCLK and SDATA signals, so that products can be designed
to respond to either USB or PS/2 modes of operation. PS/2
operation is supported with internal pull-up resistors on SCLK
and SDATA, the ability to disable the regulator output pin, and
an interrupt to signal the start of PS/2 activity. No external
components are necessary for dual USB and PS/2 systems,
and no GPIO pins need to be dedicated to switching between
modes. Slow edge rates operate in both modes to reduce EMI.
P0.5
P0.6
P0.7
P1.1
P1.3
P1.5
P1.7
D+/SCLK
D–/SDATA
VCC
P0.4
XTALOUT
USB differential data lines (D– and D+), or PS/2 clock
and data signals (SDATA and SCLK)
GPIO Port 0 capable of sinking up to 50 mA/pin, or
sinking controlled low or high programmable current.
Can also source 2 mA current, provide a resistive
pull-up, or serve as a high-impedance input. P0.0 and
P0.1 provide inputs to Capture Timers A and B, respec-
tively.
IO Port 1 capable of sinking up to 50 mA/pin, or sinking
controlled low or high programmable current. Can also
source 2 mA current, provide a resistive pull-up, or
serve as a high-impedance input.
P2.1 input
output
Programming voltage supply, ground for normal
operation
Voltage supply
nominal). Also serves as P2.0 input.
6-MHz ceramic resonator or external clock input, or
6-MHz ceramic resonator return pin or internal oscillator
Voltage supply for 1.3-kΩ USB pull-up resistor (3.3V
Ground
P0.3
P1.0
P1.2
P1.4
P1.6
VSS
VSS
Description
CY7C63722-XC
10
4
5
6
7
8
9
DIE
17
22
21
20
19
18
CY7C63722
CY7C63723
CY7C63743
P0.7
P1.1
P1.3
P1.5
P1.7
D+/SCLK
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