CY7C64013-SC Cypress Semiconductor Corp, CY7C64013-SC Datasheet - Page 20

• Manufacturer Part Number: CY7C64013-SC
• Description: IC MCU 8K FULL SPEED USB 28SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64013-SC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C640xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 19
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1327

Table 9-1. GPIO Port Output Control Truth Table and Interrupt Polarity
Port 3 Data
Special care should be taken with any unused GPIO data bits. An unused GPIO data bit, either a pin on the chip or a port bit that
is not bonded on a particular package, must not be left floating when the device enters the suspend state. If a GPIO data bit is
left floating, the leakage current caused by the floating bit may violate the suspend current limitation specified by the USB
Specifications. If a ‘1’ is written to the unused data bit and the port is configured with open drain outputs, the unused data bit
remains in an indeterminate state. Therefore, if an unused port bit is programmed in open-drain mode, it must be written with a
‘0.’ Notice that the CY7C64013 part always requires that the data bits P1[7:3], P2[7,1,0], and P3[7:3] be written with a ‘0.’
In normal non-HAPI mode, reads from a GPIO port always return the present state of the voltage at the pin, independent of the
settings in the Port Data Registers. If HAPI mode is activated for a port, reads of that port return latched data as controlled by the
HAPI signals (see Section 14.0). During reset, all of the GPIO pins are set to a high-impedance input state (‘1’ in open drain
mode). Writing a ‘0’ to a GPIO pin drives the pin LOW. In this state, a ‘0’ is always read on that GPIO pin unless an external source
overdrives the internal pull-down device.
9.1
Every GPIO port can be programmed as inputs with internal pull-ups, outputs LOW or HIGH, or Hi-Z (floating, the pin is not driven
internally). In addition, the interrupt polarity for each port can be programmed. The Port Configuration bits (Figure 9-6) and the
Interrupt Enable bit (Figure 9-7 through Figure 9-10) determine the interrupt polarity of the port pins.
GPIO Configuration
As shown in Table 9-1 below, a positive polarity on an input pin represents a rising edge interrupt (LOW to HIGH), and a negative
polarity on an input pin represents a falling edge interrupt (HIGH to LOW).
The GPIO interrupt is generated when all of the following conditions are met: the Interrupt Enable bit of the associated Port
Interrupt Enable Register is enabled, the GPIO Interrupt Enable bit of the Global Interrupt Enable Register (Figure 16-1) is
enabled, the Interrupt Enable Sense (bit 2, Figure 15-1) is set, and the GPIO pin of the port sees an event matching the interrupt
polarity.
The driving state of each GPIO pin is determined by the value written to the pin’s Data Register (Figure 9-2 through Figure 9-5)
and by its associated Port Configuration bits as shown in the GPIO Configuration Register (Figure 9-6). These ports are configured
on a per-port basis, so all pins in a given port are configured together. The possible port configurations are detailed in Table 9-1.
As shown in this table below, when a GPIO port is configured with CMOS outputs, interrupts from that port are disabled.
During reset, all of the bits in the GPIO Configuration Register are written with ‘0’ to select Hi-Z mode for all GPIO ports as the
default configuration.
Document #: 38-08001 Rev. *A
Port Config Bit 1 Port Config Bit 0 Data Register Output Drive Strength Interrupt Enable Bit
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
1
1
0
0
GPIO Configuration Port
Config Bit 1
Port 3
P3.7
R/W
R/W
7
1
7
0
1
0
1
0
Config Bit 0
Port 3
P3.6
R/W
R/W
6
1
6
0
Figure 9-6. GPIO Configuration Register
Config Bit 1
0
1
0
1
0
1
0
1
Port 2
P3.5
R/W
R/W
5
1
5
0
Figure 9-5. Port 3 Data
Config Bit 0
Output HIGH
Output LOW
Output LOW
Output LOW
Output LOW
Port 2
Resistive
P3.4
R/W
R/W
4
1
4
0
Hi-Z
Hi-Z
Config Bit 1
Port 1
P3.3
R/W
R/W
3
1
3
0
Config Bit 0
0
1
0
1
0
1
0
1
Port 1
R/W
R/W
P32
2
1
2
0
Config Bit 1
Port 0
P3.1
R/W
R/W
Interrupt Polarity
1
1
1
0
– (Falling Edge)
– (Falling Edge)
+ (Rising Edge)
CY7C64013
CY7C64113
Disabled
Disabled
Disabled
Disabled
Disabled
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ADDRESS 0x03
ADDRESS 0x08
Config Bit 0
Port 0
P3.0
R/W
R/W
0
1
0
0