CY7C65113-SC Cypress Semiconductor Corp, CY7C65113-SC Datasheet - Page 19

• Manufacturer Part Number: CY7C65113-SC
• Description: IC MCU 8K USB HUB 4 PORT 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113-SC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: SOIC
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1331

Document #: 38-08002 Rev. *D
Table 9-1. GPIO Port Output Control Truth Table and Interrupt Polarity
Q1, Q2, and Q3 discussed below are the transistors referenced in Figure 9-1. The available GPIO drive strength are:
9.2
Each GPIO pin can be individually enabled or disabled as an interrupt source. The Port 0–1 Interrupt Enable Registers provide
this feature with an Interrupt Enable bit for each GPIO pin.
During a reset, GPIO interrupts are disabled by clearing all of the GPIO Interrupt Enable bits. Writing a ‘1’ to a GPIO Interrupt
Enable bit enables GPIO interrupts from the corresponding input pin. All GPIO pins share a common interrupt, as discussed in
Section 14.7.
.
10.0
The 12-bit timer operates with a 1-µs tick, provides two interrupts (128 µs and 1.024 ms) and allows the firmware to directly time
events that are up to 4 ms in duration. The lower eight bits of the timer can be read directly by the firmware. Reading the lower
eight bits latches the upper four bits into a temporary register. When the firmware reads the upper four bits of the timer, it is actually
reading the count stored in the temporary register. The effect of this is to ensure a stable 12-bit timer value can be read, even
when the two reads are separated in time.
Port Config Bit 1 Port Config Bit 0 Data Register Output Drive Strength Interrupt Enable Bit
Port 0 Interrupt Enable
Bit #
Bit Name
Read/Write
Reset
Port 1 Interrupt Enable
Bit #
Bit Name
Read/Write
Reset
• Output LOW Mode: The pin’s Data Register is set to ‘0.’
• Output HIGH Mode: The pin’s Data Register is set to 1 and the Port Configuration Bits[1:0] is set to ‘10.’
• Resistive Mode: The pin’s Data Register is set to 1 and the Port Configuration Bits[1:0] is set to ‘11.’
• Hi-Z Mode: The pin’s Data Register is set to1 and Port Configuration Bits[1:0] is set either ‘00’ or ‘01.’
Writing ‘0’ to the pin’s Data Register puts the pin in output LOW mode, regardless of the contents of the Port Configuration
Bits[1:0]. In this mode, Q1 and Q2 are OFF. Q3 is ON. The GPIO pin is driven LOW through Q3.
In this mode, Q1 and Q3 are OFF. Q2 is ON. The GPIO is pulled up through Q2. The GPIO pin is capable of sourcing... of
current.
Q2 and Q3 are OFF. Q1 is ON. The GPIO pin is pulled up with an internal 14kΩ resistor. In resistive mode, the pin may serve
as an input. Reading the pin’s Data Register returns a logic HIGH if the pin is not driven LOW by an external source.
Q1, Q2, and Q3 are all OFF. The GPIO pin is not driven internally. In this mode, the pin may serve as an input. Reading the
Port Data Register returns the actual logic value on the port pins.
1
1
0
0
GPIO Interrupt Enable Ports
12-bit Free-Running Timer
Reserved
P0.7 Intr
Enable
W
7
7
0
-
-
1
0
1
0
Reserved
P0.6 Intr
Enable
W
6
6
0
-
-
Reserved
0
1
0
1
0
1
0
1
P0.5 Intr
Figure 9-5. Port 0 Interrupt Enable
Figure 9-6. Port 1 Interrupt Enable
Enable
W
5
0
5
-
-
Reserved
P0.4 Intr
Output HIGH
Output LOW
Output LOW
Output LOW
Output LOW
Enable
Resistive
W
4
0
4
-
-
Hi-Z
Hi-Z
Reserved
P0.3 Intr
Enable
W
3
0
3
-
-
P0.2 Intr
P0.2 Intr
Enable
Enable
0
1
0
1
0
1
0
1
W
W
2
0
2
0
P0.1 Intr
P1.1 Intr
Enable
Enable
CY7C65113C
W
W
Interrupt Polarity
1
0
1
0
– (Falling Edge)
– (Falling Edge)
+ (Rising Edge)
Disabled
Disabled
Disabled
Disabled
Disabled
Address 0x04
Address 0x05
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P0.0 Intr
P1.0 Intr
Enable
Enable
W
W
0
0
0
0