CY7C65113-SC Cypress Semiconductor Corp, CY7C65113-SC Datasheet - Page 22

• Manufacturer Part Number: CY7C65113-SC
• Description: IC MCU 8K USB HUB 4 PORT 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113-SC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: SOIC
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1331

11.0
Internal hardware supports communication with external devices through an I
discussed in detail in Section 12.0.
locations of the SCL (clock) and SDA (data) pins, either on Port 1 or Port 2 as shown in Table 11-1. These bits are cleared on
reset. When the GPIO is configured for I
pull-up resistors on SCL and SDA is recommended
.
Table 11-1. I
12.0
The I2C-compatible block provides a versatile two-wire communication with external devices, supporting master, slave, and
multi-master modes of operation. The I2C-compatible block functions by handling the low-level signaling in hardware, and issuing
interrupts as needed to allow firmware to take appropriate action during transactions. While waiting for firmware response, the
hardware keeps the I2C-compatible bus idle if necessary.
The I2C-compatible block generates an interrupt to the microcontroller at the end of each received or transmitted byte, when a
stop bit is detected by the slave when in receive mode, or when arbitration is lost. Details of the interrupt responses are given in
Section 14.8.
The I2C-compatible interface consists of two registers, an I
(Figure 12-2). The I
Register should only be monitored after the I
read misleading bit status if a transaction is underway.
Note:
Document #: 38-08002 Rev. *B
I
Bit #
Bit Name
Read/Write
Reset
3.
2
C Configuration
I
2
C-compatible function must be separately enabled, as described in Section 12.0.
I
2
C Position (Bit7, Figure 11-1)
I2C-compatible Controller
I
2
C Configuration Register
11
L3
2
C Port Configuration
I
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
2
C Position
Don’t Care
R/W
10 9
L2
2
C Data Register is implemented as separate read and write registers. Generally, the I
7
0
0
1
L1 L0
Reserved
8
R/W
[3]
6
0
The I
Figure 10-3. Timer Block Diagram
7
2
C function, the internal pull ups on the pins are disabled. Addition of an external weak
2
Figure 11-1. I
C Position bit (Bit 7, Figure 11-1) and I
2
6
Reserved
C interrupt, as all bits are valid at that time. Polling this register at other times could
R/W
5
0
I
2
C Port Width (Bit1, Figure 11-1)
5
2
4
C Configuration Register
2
Reserved
C Data Register (Figure 12-1) and an I
R/W
4
0
3
1
0
0
2
Reserved
R/W
1
2
3
0
C-compatible interface. I
2
C Port Width bit (Bit 1, Figure 11-1) select the
0
8
Reserved
R/W
2
0
1.024-ms interrupt
128- s interrupt
I
I
I
2
2
2
1 MHz clock
To Timer Registers
C on P2[1:0], 0:SCL, 1:SDA
C on P1[1:0], 0:SCL, 1:SDA
C on P2[1:0], 0:SCL, 1:SDA
2
C Status and Control Register
I
2
2
I
2
C Position
C-compatible function is
Width
C Port
R/W
2
1
0
C Status and Control
CY7C65013
CY7C65113
Address 0x09
Page 22 of 51
Reserved
R/W
0
0