CY7C65113-SC Cypress Semiconductor Corp, CY7C65113-SC Datasheet - Page 33

• Manufacturer Part Number: CY7C65113-SC
• Description: IC MCU 8K USB HUB 4 PORT 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113-SC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: SOIC
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1331

Table 16-1. Control Bit Definition for Downstream Ports
An alternate means of forcing the downstream ports is through the Hub Ports Force Low Register (Figure 16-5) and Hub Ports
Force High Register (Figure 16-6). With these registers the pins of the downstream ports can be individually forced LOW, or left
unforced. Unlike the Hub Downstream Ports Control Register, above, the Force Low Register does not produce standard USB
edge rate control on the forced pins. However, this register allows downstream port pins to be held LOW in suspend. This register
can be used to drive SE0 on all downstream ports when unconfigured, as required in the USB 1.1 specification
.
The data state of downstream ports can be read through the HUB Ports SE0 Status Register (Figure 16-7) and the Hub Ports
Data Register (Figure 16-8). The data read from the Hub Ports Data Register is the differential data only and is independent of
the settings of the Hub Ports Speed Register (Figure 16-2). When the SE0 condition is sensed on a downstream port, the
corresponding bits of the Hub Ports Data Register hold the last differential data state before the SE0. Hub Ports SE0 Status
Register and Hub Ports Data Register are cleared upon reset or bus reset
.
Document #: 38-08002 Rev. *B
Hub Ports Force Low
Bit #
Bit Name
Read/Write
Reset
Hub Ports Force Low
Bit #
Bit Name
Read/Write
Reset
Hub Downstream Ports Control Register
Bit #
Bit Name
Read/Write
Reset
Hub Ports SE0 Status
Bit #
Bit Name
Read/Write
Reset
Bit1
Control Bits
0
0
1
1
Bit 0
0
1
0
1
Control Bit 1
Force Low
Reserved
Reserved
D+[4]
Port 4
Not Forcing (Normal USB Function)
Force Differential ‘1’ (D+ HIGH, D– LOW)
Force Differential ‘0’ (D+ LOW, D– HIGH)
Force SE0 state
R/W
R/W
7
0
7
–
–
R
7
0
7
0
Control Bit 0
Force Low
Reserved
SE0 Status
D-[4]
Port 7
Port 4
R/W
R/W
6
–
–
6
0
R
6
0
6
0
Control Action
Figure 16-4. Hub Downstream Ports Control Register
Figure 16-7. Hub Ports SE0 Status Register
Figure 16-5. Hub Ports Force Low Register
Figure 16-6. Hub Ports Force Low Register
Force Low
Control Bit 1
Force Low
SE0 Status
D+[7]
D+[3]
R/W
Port 6
R/W
Port 3
R/W
5
0
5
0
R
5
0
5
0
Force Low
Control Bit 0
Force Low
SE0 Status
D–[7]
D–[3]
R/W
Port 5
Port 3
R/W
R/W
4
0
4
0
R
4
0
4
0
Force Low
Control Bit 1
Force Low
SE0 Status
D+[6]
D+[2]
Port 4
R/W
Port 2
R/W
R/W
3
0
3
0
R
3
0
3
0
Control Bit 0
SE0 Status
Force Low
Force Low
D–[6]
Port 3
D–[2]
Port 2
R/W
R/W
R/W
2
0
2
0
R
2
0
2
0
SE0 Status
Control Bit 1
Force Low
Force Low
Port 2
D+[1]
D+[5]
Port 1
R/W
R/W
R/W
R
1
0
1
0
1
0
1
0
Address 0x4F
CY7C65013
CY7C65113
Address 0x4B
Address 0x51
Address 0x52
Page 33 of 51
SE0 Status
Force Low
Force Low
Control Bit
Port 1
Port 1
D–[1]
D–[5]
R/W
R/W
R/W
R
0
0
0
0
0
0
0
0
0