CY7C53120E2-10SXIT Cypress Semiconductor Corp, CY7C53120E2-10SXIT Datasheet
CY7C53120E2-10SXIT
Specifications of CY7C53120E2-10SXIT
Related parts for CY7C53120E2-10SXIT
CY7C53120E2-10SXIT Summary of contents
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... Junction Cypress Semiconductor Corporation Document #: 38-10001 Rev. *E ® Neuron Chip Network Processor • (CY7C53120E2 (CY7C53120E4) of ROM containing LonTalk • Maximum input clock operation of 20 MHz (CY7C53150), 10 MHz (CY7C53120E2), 40 MHz (CY7C53120E4) over a [2] –40°C to 85°C • 64-pin TQFP package (CY7C53150) • ...
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... The CY7C53150 Neuron chip is an exact replacement for the Motorola MC143150Bx and Toshiba TMPN3150B1 devices. The CY7C53120E2 Neuron chip is an exact replacement for the Motorola MC143120E2 device since it contains the same firmware in ROM. CY7C53150 ...
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Pin Configurations (continued) 32-lead SOIC RESET IO4 3 30 IO5 IO3 4 29 IO6 IO2 5 28 IO7 IO1 6 27 IO8 IO0 7 26 IO9 SERVICE ...
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Pin Descriptions Pin Name IO CLK1 Input Oscillator connection or external clock input. CLK2 Output Oscillator connection. Leave open when external clock is input to CLK1. Maximum of one external load. RESET IO (Built-In Reset pin (active LOW). Note The ...
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Memory Usage All Neuron chips require system firmware to be present when they are powered up. In the case of the CY7C53120 family, this firmware is preprogrammed in the factory in an on-chip ROM. In the case of the CY7C53150, ...
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Programmable Hysteresis Values (Expressed as differential peak-to-peak voltages in terms of V [6] Hysteresis V Min. V Typ. hys hys 0 0.019 V 0.027 0.040 V 0.054 0.061 V 0.081 0.081 ...
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... LVI Trip Point ( Part Number CY7C53120E2, CY7C53120E4, and CY7C53150 Notes 11. Standard outputs are IO4–IO10, CP0, CP1, and CP4. (RESET is an open drain input/output. CLK2 must have < load.) For CY7C53150, standard outputs also include A0–A15, D0–D7, E, and R/W. 12. IO4–IO7 and SERVICE have configurable pull ups. RESET has a permanent pull up. ...
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External Memory Interface Timing — CY7C53150, V Parameter t Memory Cycle Time (System Clock Period) cyc [16] PW Pulse Width, E High EH [16] PW Pulse Width, E Low EL t Delay, E High to Address Valid AD t Address ...
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Figure 4. Drive Levels and Test Point Levels for Timing Specifications Unless Otherwise Specified DRIVE TO 2.4V DRIVE TO 0.4V A — Signal valid-to-signal valid specification (maximum or minimum) B — Signal valid-to-signal invalid specification (maximum or minimum) Figure 5. ...
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... CY7C53120E4-40AXI 4 Notes 23. All parts contain SRAM. 24. CY7C53120E2 firmware is bit-for-bit identical with Motorola MC143120E2 firmware. 25. CY7C53150 may be used with 20-MHz input clock only if the firmware in external memory is version 13 or later. 26. CY7C53120E4 requires upgraded LonBuilder® and NodeBuilder® software. Document #: 38-10001 Rev trip - Max ...
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Package Diagrams Figure 9. 44-Lead Thin Plastic Quad Flat Pack A44 12.00±0.25 SQ 10.00±0. SEATING PLANE 1.60 MAX. 0.10 0.20 MAX. Document #: 38-10001 Rev 0.37±0.05 STAND-OFF 0.05 MIN. 0.15 MAX. 0.80 ...
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Package Diagrams (continued) Figure 10. 64-Lead Thin Plastic Quad Flat Pack ( 1.4 mm) A64SA 16.00±0.25 SQ 14.00±0. SEATING PLANE 1.60 MAX. 0.10 0.20 MAX Document #: 38-10001 Rev. *E NOTE: 1. ...
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... Document #: 38-10001 Rev. *E © Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...
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Document History Page Document Title: CY7C53150/CY7C53120 Neuron Document Number: 38-10001 Orig. of REV. ECN NO. Issue Date Change ** 111472 11/28/01 DSG *A 111990 02/06/02 *B 114465 04/24/02 *C 115269 04/26/02 *D 124450 03/25/03 *E 837840 3/14/07 BOO Document #: ...